FS781/82/84
Low EMI Spectrum Spread Clock
Features
• Spread Spectrum clock generator (SSCG) with 1×, 2×,
and 4× outputs
• 6- to 82-MHz operating frequency range
• Modulates external clocks including crystals, crystal
oscillators, or ceramic resonators
• Programmable modulation with simple R-C external
loop filter (LF)
• Center spread modulation
• 3V-5V power supply
• TTL-/CMOS-compatible outputs
• Low short-term jitter
• Low-power Dissipation
— 3.3 VDC = 37 mW – typical
— 5.0 VDC = 115 mW – typical
• Available in 8-pin SOIC and TSSOP packages
Functional Description
The Cypress FS781/82/84 are Spread Spectrum clock
generator ICs (SSCG) designed for the purpose of reducing
electromagnetic interference (EMI) found in today’s
high-speed digital systems.
The FS781/82/84 SSCG clocks use a Cypress-proprietary
technology to modulate the input clock frequency, XIN, by
modulating the frequency of the digital clock. By modulating
the reference clock the measured EMI at the fundamental and
harmonic frequencies of FSOUT is greatly reduced. This
reduction in radiated energy can significantly reduce the cost
of complying with regulatory requirements without degrading
digital waveforms.
The Cypress FS781/82/84 clocks are very simple and
versatile devices to use. By programming the two range select
lines, S0 and S1, any frequency from 6- to 82-MHz operating
range can be selected. The FS781/2/4 are designed to
operate over a very wide range of input frequencies and
provides 1×, 2×, and 4× modulated clock outputs.
The FS78x devices have a simple frequency selection table
that allows operation from 6 MHz to 82 MHz in four separate
ranges. The bandwidth of the frequency spread at FSOUT is
determined by the values of the loop filter components. The
modulation rate is determined internally by the input frequency
and the selected input frequency range.
The Bandwidth of these products can be programmed from as
little as 1.0% up to as much as 4.0% by selecting the proper
loop filter value. Refer to the Loop Filter Selection chart in
Table 2
and
Table 3
for the recommended values. Due to a
wide range of application requirements, an external loop filter
(LF) is used on the FS78x products. The user can select the
exact amount of frequency modulation suitable for the appli-
cation. Using a fixed internal loop filter would severely limit
the use of a wide range of modulation bandwidths (Spread %)
to a few discrete values. Refer to FS791/2/4 products for appli-
cations requiring 80- to 140-MHz frequency range.
Applications
• Desktop/notebook computers
• Printers, copiers, and MFP
• Scanners and fax
• LCD displays and monitors
• CD-ROM, VCD, and DVD
• Automotive and embedded systems
• Networking, LAN/WAN
• Digital cameras and camcorders
• Modems
Benefits
• Programmable EMI reduction
• Fast time to market
• Lower cost of compliance
• No degradation in rise/fall times
• Lower component and PCB layer count
Cypress Semiconductor Corporation
Document #: 38-07029 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 2, 2005
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FS781/82/84
Block Diagram
Loop Filter
4(6)
250 K
Pin Configuration
Xin
Xout
Reference
Divider
1
2
3
4
FS78x
8
7
6
5
VDD
S0
FSOUT
VSS
S1
Phase
Detector
VCO
10 pF.
Xin
1(3)
8 pF
LF
Xout
Modulation
Control
2(4)
8 Pin SOIC Package
8 pF
VCO / N
S0
VDD
8(2)
1
2
3
4
FS78x
8
7
6
5
FSOUT
VSS
LF
S1
Power Contol
Logic
VDD
Input Control Logic
Output
Divider
and
Mux
VSS
VDD
6(8)
FSOUT
Xin
Xout
5(7)
3(5)
7(1)
(TSSOP Pin #)
VSS
S1
S0
8 Pin TSSOP Package
Pin Description
Pin
1/2 (SOIC)
3/4 (TSSOP)
Name
X
IN
/X
OUT
I/O
I/O
Type
Analog
Description
Pins form an on-chip reference oscillator when connected to terminals
of an external parallel resonant crystal.
X
IN
may be connected to
TTL/CMOS external clock source. If X
IN
is connected to an external clock
other than crystal, leave X
OUT
(pin 2) unconnected.
7/3 (SOIC)
1/5 (TSSOP)
4 (SOIC)
6 (TSSOP)
6 (SOIC)
8 (TSSOP)
8 (SOIC)
2 (TSSOP)
5 (SOIC)
7 (TSSOP)
S0 / S1
I
CMOS/TTL
Digital control inputs to select input frequency range and output
frequency scaling.
Refer to
Table 2
and
Table 3
for selection. S0 has internal
pull-down. S1 has internal pull-up.
Analog
Loop Filter.
Single ended three-state output of the phase detector. A two-pole
passive loop filter is connected to LF.
LF
FSOUT
I
O
CMOS/TTL
Modulated Clock Frequency Output.
The center frequency is the same as
the input reference frequency for FS781. Input frequency is multiplied by 2×
and 4× for FS782 and FS784, respectively.
Power
Power
Positive Power Supply.
Power Supply Ground.
V
DD
V
SS
P
P
Output Frequency Selection
Table 1. FSOUT SSCG (Modulated Output Clock) Product Selection
Product Number
FS781
FS782
FS784
FSOUT Frequency Scaling
1×
2×
4×
Description
1× modulated frequency of input clock
2× modulated frequency of input clock
4× modulated frequency of input clock
R6
Loop Filter Selection Chart
The following table provides a list of recommended loop filter
values for the FS781/82/84. The FS78X is divided into four
ranges and operated at both 3.3V and 5.5 VDC. The loop filter
at the right is representative of the loop filter components in
Table 2.
LF (pin 4)
C8
C7
Document #: 38-07029 Rev. *F
Page 2 of 12
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FS781/82/84
Table 2. FS781/82/84 Recommended Loop Filter Values
C7 (pF) @ +3.3 VDC ±5% (R6 = 3.3K)
[1, 2, 3, 4]
Input MHz S1
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
65
66
68
70
72
74
76
78
80
82
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
BW = 1.0%
[3]
10,000/1000
10,000/330
1040
830
580
10000
1200
1000
960
920
660
470
470
330
10000
2200
1500
960
940
950
900
790
660
470
470
445
430
295
270
1180
1180
1180
1180
1120
1160
1110
1000
910
900
900
BW = 1.5%
[3]
BW = 2.0%
[3]
BW = 2.5%
[3]
BW = 3.0%
[3]
BW = 3.5%
[3]
BW = 4.0%
[3]
1550
990
680
420
230
980
750
730
640
400
300
230
180
170
860
820
690
600
620
680
580
440
360
325
270
250
210
185
220
860
850
760
750
740
780
770
720
670
620
540
910
820
460
300
200
760
580
470
410
250
220
180
140
120
640
620
520
420
380
400
270
260
250
220
200
185
165
150
150
560
540
560
500
470
470
470
440
270
260
250
780
640
360
220
160
580
470
390
270
210
180
150
120
100
520
470
410
340
275
250
220
210
190
185
170
150
130
120
120
410
400
350
320
370
300
280
240
210
210
210
700
520
300
200
140
470
415
320
230
180
150
130
100
82
430
400
340
280
230
210
190
180
170
155
140
120
100
100
100
340
330
260
260
300
250
230
210
190
190
190
640
450
240
190
100
410
370
220
200
160
140
100
80
68
380
330
290
220
210
190
180
160
150
135
130
85
65
90
82
290
280
220
230
240
220
210
190
170
170
170
560
400
210
170
80
385
300
190
180
150
120
70
60
47
330
290
240
160
180
170
165
140
140
120
100
47
33
82
68
230
220
210
210
170
190
190
170
160
156
150
Notes:
1. If the value selected from the above chart is not a standard, use the next available larger value.
2. All bandwidths indicated above are total peak-to-peak spread. 1% = +0.5% to –0.5%. 4% = +2.0% to –2.0%.
3. If C8 is not listed in the chart for a particular bandwidth and frequency, it is not used in the loop filter.
4. Contact Cypress for LF values less than 1.0% bandwidth.
Document #: 38-07029 Rev. *F
Page 3 of 12
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FS781/82/84
Table 3. FS781/82/84 Recommended Loop Filter Values
C7 (pF) @ +5.0 VDC ±5% (R6 = 3.3K)
[1, 2, 3, 4]
Input MHz
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
S1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
BW = 1.0%
[3]
BW = 1.5%
[3]
BW = 2.0%
[3]
BW = 2.5%
[3]
BW = 3.0%
[3]
BW = 3.5%
[3]
BW = 4.0%
[3]
1140
1170
1030
760
450
2490
2490
1360
990
820
530
430
250
Note 4
Note 4
Note 4
Note 4
Note 4
1030
790
1110
1110
830
560
510
470
450
430
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
1030
970
660
340
240
970
870
680
560
360
270
230
200
1000
990
970
880
800
680
560
420
280
330
340
280
210
220
240
800
720
630
690
650
575
500
550
600
570
540
930
740
430
230
180
730
650
480
330
250
210
180
150
740
710
670
560
460
360
260
280
200
200
205
180
160
250
120
580
490
400
365
330
340
355
330
290
240
250
830
570
350
200
140
590
510
370
260
200
170
150
110
570
520
480
380
290
260
220
210
190
180
170
140
120
110
90
430
375
320
285
250
250
245
230
220
210
200
710
460
280
180
100
480
430
280
230
180
150
110
100
470
420
380
310
240
220
200
180
170
160
140
110
100
90
80
330
285
240
225
210
210
205
200
190
185
180
610
400
210
160
70
430
370
190
200
160
110
100
90
410
360
310
270
230
200
190
170
140
130
120
110
90
80
80
250
200
150
170
190
190
180
175
170
165
160
510
280
130
130
50
370
310
250
190
150
90
90
80
370
300
230
220
220
190
170
140
120
110
90
90
90
80
70
180
140
100
140
180
170
165
160
155
150
140
Document #: 38-07029 Rev. *F
Page 4 of 12
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FS781/82/84
Table 4. Modulation Rate Divider Ratios
S1
0
0
1
1
S0
0
1
0
1
Input Frequency Range (MHz)
6 to 16
16 to 32
32 to 66
66 to 82
Modulation Divider Number
120
240
480
720
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multi-layer PCBs, etc. These FS781/2 and 4 reduce the peak
energy in the clock by increasing the clock bandwidth and
lowering the Q of the clock.
SSCG Modulation Profile
The digital control inputs S0 and S1 determine the modulation
frequency of FS781/2/4 products. The input frequency is
divided by a fixed number, depending on the operating range
that is selected. The modulation frequency of the FS78x can
be determined from
Table 4.
To compute the modulation
frequency, determine the values of S0 and S1, and find the
modulation divider number in
Table 4.
Theory of Operation
The FS781/82/84 devices are phase-locked loop-(PLL)-type
clock generators using Direct Digital Synthesis (DDS). ‘By
precisely controlling the bandwidth of the output clock, the
FS781/2/4 products become a low-EMI clock generator. The
theory and detailed operation of these products will be
discussed in the following sections.
SSCG
The FS781/82/84 products use a unique method of modulating
the clock over a very narrow bandwidth and controlled rate of
change, both peak to peak and cycle to cycle. The FS78x
products take a narrow band digital reference clock in the
range of 6–82 MHz and produce a clock that sweeps between
a controlled start and stop frequency and precise rate of
change. To understand what happens to an SSCG clock,
consider that we have a 20-MHz clock with a 50% duty cycle.
From a 20-MHz clock we know the following:
Clock Frequency = Fc = 20 MHz.
Clock Period = Tc = 1/20 MHz = 50 ns.
Consider that this 20-MHz clock is applied to the X
IN
input of
the FS78x as either an externally driven clock or the result of
a parallel resonant crystal connected to pins 1 and 2 of the
FS78x. Also consider that the products are operating from a
5V DC power supply and the loop filter is set for a total
bandwidth spread of 2%. Refer to
Figure 2.
EMI
All clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of the 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics (e.g., third, fifth, seventh). It is possible to
reduce the amount of energy contained in the fundamental
and harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
+ .5%
1.0%
Xin
Total
- .5%
TIME (microseconds)
Figure 1. Frequency Profile in Time Domain
[5]
Note:
5. With the correct loop filter connected to Pin 4, the following profile will provide the best EMI reduction. This profile can be seen on a Time Domain Analyzer.
Document #: 38-07029 Rev. *F
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