BUK9675-100A
18 August 2015
D2
PA
K
N-channel TrenchMOS logic level FET
Product data sheet
1. General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
2. Features and benefits
•
•
AEC Q101 compliant
Low conduction losses due to low on-state resistance
3. Applications
•
Automotive and general purpose power switching
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 12
V
GS
= 5 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 12
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-
source avalanche
energy
[1]
[2]
Min
-
-
-
Typ
-
-
-
Max
100
23
98
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
-
-
55
60
72
75
mΩ
mΩ
I
D
= 23 A; V
sup
≤ 100 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
Fig. 4
[1][2]
-
-
100
mJ
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
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NXP Semiconductors
BUK9675-100A
N-channel TrenchMOS logic level FET
5. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to
drain
2
1
3
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
D2PAK (SOT404)
6. Ordering information
Table 3.
Ordering information
Package
Name
BUK9675-100A
D2PAK
Description
plastic single-ended surface-mounted package
(D2PAK); 3 leads (one lead cropped)
Version
SOT404
Type number
7. Marking
Table 4.
Marking codes
Marking code
BUK9675-100A
Type number
BUK9675-100A
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
P
tot
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
T
mb
= 25 °C;
Fig. 1
T
mb
= 100 °C; V
GS
= 5 V;
Fig. 2
T
mb
= 25 °C; V
GS
= 5 V;
Fig. 2
I
DM
T
stg
T
j
BUK9675-100A
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ
Min
-
-
-15
-
-
-
-
-55
-55
Max
100
100
15
98
16
23
92
175
175
Unit
V
V
V
W
A
A
A
°C
°C
2 / 12
peak drain current
storage temperature
junction temperature
T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 3
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet
18 August 2015
NXP Semiconductors
BUK9675-100A
N-channel TrenchMOS logic level FET
Symbol
I
S
I
SM
E
DS(AL)S
Parameter
source current
peak source current
Conditions
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 23 A; V
sup
≤ 100 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
Fig. 4
Min
-
-
Max
23
92
Unit
A
A
Source-drain diode
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
[1][2]
-
100
mJ
[1]
[2]
120
P
der
(%)
80
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
03aa16
I
D
(A)
25
aaa-019260
20
15
10
40
5
0
0
50
100
150
T
mb
(°C)
200
0
0
25
50
75
100
125
150 175
T
mb
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
V
GS
≥ 5V
Fig. 2.
Continuous drain current as a function of
mounting base temperature
BUK9675-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet
18 August 2015
3 / 12
NXP Semiconductors
BUK9675-100A
N-channel TrenchMOS logic level FET
10
3
I
DM
(A)
10
2
R
DS(on)
= V
DS
/ I
D
003aaf172
I
AL
(A)
10
2
003aaf188
10
(1)
tp = 1 µs
10 µs
10
D.C.
1
1
10
100 µs
1 ms
10 ms
10
2
V
DS
(V)
10
3
10
-1
1
(3)
(2)
T
mb
= 25 °C; I
DM
is single pulse
Fig. 3.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
10
-2
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
(1) T
j (init)
= 25°C; (2) T
j (init)
= 150°C; (3) Repetitive
Avalanche
Fig. 4.
Avalanche rating; avalanche current as a
function of avalanche time
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
10
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.05
0.02
0
10
- 2
10
- 6
10
- 5
10
- 4
10
- 3
P
δ=
t
p
T
Conditions
Min
-
Typ
-
Max
1.5
Unit
K/W
R
th(j-a)
Minimum footprint; FR4 board
-
50
-
K/W
003aaf173
10
- 1
t
p
10
- 2
t
T
10
- 1
1
t
p
(s)
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9675-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet
18 August 2015
4 / 12
NXP Semiconductors
BUK9675-100A
N-channel TrenchMOS logic level FET
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 10; Fig. 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 10
I
DSS
drain leakage current
V
DS
= 100 V; V
GS
= 0 V; T
j
= 175 °C
V
DS
= 100 V; V
GS
= 0 V; T
j
= 25 °C
I
GSS
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 10 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 12
V
GS
= 5 V; I
D
= 10 A; T
j
= 175 °C;
Fig. 13
V
GS
= 4.5 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 12
V
GS
= 5 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 12
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
L
D
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain
inductance
from drain lead 6 mm from package to
centre of die; T
j
= 25 °C
All information provided in this document is subject to legal disclaimers.
Min
100
89
0.5
1
-
-
-
-
-
-
-
-
-
Typ
-
-
-
1.5
-
-
0.05
2
2
55
-
61
60
Max
-
-
-
2
2.3
500
10
100
100
72
188
84
75
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
mΩ
Static characteristics
V
GS(th)
I
D
= 10 A; V
DS
= 80 V; V
GS
= 5 V;
Fig. 14; Fig. 15
-
-
-
24.3
3
12.2
1278
129
88
13
120
58
57
4.5
-
-
-
1704
155
120
20
168
87
86
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
T
j
= 25 °C;
Fig. 16
-
-
-
V
DS
= 30 V; R
L
= 1.2 Ω; V
GS
= 5 V;
R
G(ext)
= 10 Ω; T
j
= 25 °C
-
-
-
-
-
BUK9675-100A
© NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet
18 August 2015
5 / 12
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