BUK964R7-80E
13 March 2014
D2
PA
K
N-channel TrenchMOS logic level FET
Product data sheet
1. General description
Logic level N-channel MOSFET in a SOT404 package using TrenchMOS technology.
This product has been designed and qualified to AEC Q101 standard for use in high
performance automotive applications.
2. Features and benefits
•
•
•
•
AEC Q101 compliant
Repetitive avalanche rated
Suitable for thermally demanding environments due to 175 °C rating
True logic level gate with Vgst(th) rating of greater than 0.5V at 175 °C
3. Applications
•
•
•
•
•
12V, 24V and 48V Automotive systems
Motors, lamps and solenoid control
Start-Stop micro-hybrid applications
Transmission control
Ultra high performance power switching
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
[1]
Min
-
-
-
Typ
-
-
-
Max
80
120
324
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
gate-drain charge
-
3.6
4.7
mΩ
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 25 A; V
DS
= 64 V;
Fig. 13; Fig. 14
[1]
Continuous current is limited by package.
-
28.9
-
nC
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NXP Semiconductors
BUK964R7-80E
N-channel TrenchMOS logic level FET
5. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to
drain
2
1
3
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
D2PAK (SOT404)
6. Ordering information
Table 3.
Ordering information
Package
Name
BUK964R7-80E
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
7. Marking
Table 4.
Marking codes
Marking code
BUK964R7-80E
Type number
BUK964R7-80E
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ
T
j
≤ 175 °C; Pulsed
T
j
≤ 175 °C; DC
P
tot
I
D
total power dissipation
drain current
T
mb
= 25 °C;
Fig. 1
T
mb
= 25 °C; V
GS
= 5 V;
Fig. 2
T
mb
= 100 °C; V
GS
= 5 V;
Fig. 2
I
DM
T
stg
BUK964R7-80E
Min
-
-
[1][2]
Max
80
80
15
10
324
120
120
667
175
Unit
V
V
V
V
W
A
A
A
°C
2 / 13
-15
-10
-
[3]
[3]
-
-
-
-55
peak drain current
storage temperature
T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 3
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
NXP Semiconductors
BUK964R7-80E
N-channel TrenchMOS logic level FET
Symbol
T
j
I
S
I
SM
E
DS(AL)S
Parameter
junction temperature
Conditions
Min
-55
Max
175
Unit
°C
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 120 A; V
sup
≤ 80 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
Fig. 4
[1]
[2]
[3]
[4]
[5]
120
P
der
(%)
80
[3]
-
-
120
667
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
[4][5]
-
384
mJ
Accumulated pulse duration up to 50 hours delivers zero defect ppm
Significantly longer life times are achieved by lowering T
j
and or V
GS
Continuous current is limited by package.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
03aa16
200
I
D
(A)
160
003aah915
120
(1)
80
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(° C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
(1) Capped at 120A due to package
Fig. 2.
Continuous drain current as a function of
mounting base temperature
BUK964R7-80E
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
3 / 13
NXP Semiconductors
BUK964R7-80E
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
003aah917
Limit R
DSon
= V
DS
/ I
D
t
p
=10 µ s
100 µ s
10
DC
1
1 ms
10 ms
100 ms
10
-1
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
10
3
I
AL
(A)
10
2
003aah916
(1)
10
(2)
1
(3)
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig. 4.
Avalanche rating; avalanche current as a function of avalanche time
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
Conditions
Fig. 5
Min
-
Typ
-
Max
0.46
Unit
K/W
R
th(j-a)
minimum footprint ; mounted on a
printed-circuit board
-
50
-
K/W
BUK964R7-80E
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
4 / 13
NXP Semiconductors
BUK964R7-80E
N-channel TrenchMOS logic level FET
1
Z
th(j-mb)
(K/W) δ = 0.5
10
-1
0.2
0.1
0.05
10
-2
003aah663
0.02
single shot
P
δ=
t
p
T
t
p
t
T
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 9; Fig. 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 9
I
DSS
drain leakage current
V
DS
= 80 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 80 V; V
GS
= 0 V; T
j
= 175 °C
I
GSS
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 5 V; I
D
= 25 A; T
j
= 175 °C;
Fig. 12; Fig. 11
Dynamic characteristics
Q
G(tot)
Q
GS
BUK964R7-80E
Min
80
72
1.4
-
0.5
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
0.13
-
2
2
3.6
3.3
-
Max
-
-
2.1
2.45
-
1
500
100
100
4.7
4.5
11.7
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
V
GS(th)
total gate charge
gate-source charge
I
D
= 25 A; V
DS
= 64 V; V
GS
= 5 V;
Fig. 13; Fig. 14
All information provided in this document is subject to legal disclaimers.
-
-
92.1
25.7
-
-
nC
nC
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
5 / 13
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