Ordering number : ENN*7371
CMOS IC
LC87F6032A
8 bit Single Chip Microcontroller with
32K-Byte FROM and 768-Byte RAM on Chip
Preliminary
Overview
The LC87F6032A is an 8-bit single chip
microcontroller with the following one-chip features :
• CPU : Operable at a minimum bus cycle time of 100 ns
• on-chip Flash ROM Capacity : 32K bytes
(on-board rewritable)
• on-chip RAM Capacity : 768 bytes
• VFD automatic display controller / driver
• 16-bit timer / counter
(can be divided into two 8 bit timers)
• system clock divider
• synchronous serial I/O port
(with automatic block transmit / receive function)
• asynchronous / synchronous serial I/O port
• 8-channel × 8-bit AD converter
• 11-source 9-vectored interrupt system
Package Dimensions
unit: mm
3159A
[ LC87F6032A ]
Features
(1) Read Only Memory (Flash ROM)
• single 5V power supply, on-board rewritable
• block erase in 128 byte units
• 32768 × 8 bits (LC87F6032A)
(2) Random Access Memory (RAM) : 768 × 9 bits
(LC87F6032A)
(3) Minimum Bus Cycle Time : 100 ns (10MHz)
Note: Bus cycle time indicates the speed to read ROM.
(4) Minimum Instruction Cycle Time : 300 ns (10MHz)
*This product incorporates technology licensed from Silicon Storage Technology Inc
Ver.1.00
N0501
22504 TN IM NO No.7371-1/16
LC87F6032A
(5) Ports
• Input / output ports
Input / output programmable for each bit individually :
9 (P1n, P70)
Data direction programmable in nibble units :
8 (P0n)
(When N-channel open drain output is selected, data can be input by bit.)
• VFD output ports
Large current outputs for digits :
9 (S0 / T0 to S8 / T8)
Large current outputs for digits / segments :
7 (S9 / T9 to S15 / T15)
digit / segment outputs :
8 (S16 to S23)
segment outputs :
16 (S24 to S39)
Other function
Input ports :
16 (PCn, PDn,)
• Oscillator pins :
2 (CF1, CF2)
• Reset pin :
1 (RES#)
• Power supply :
3 (VSS1, VDD1, VDD2)
• VFD power supply :
1 (VP)
(6) VFD automatic display controller
• Programmable segment / digit output pattern
Output can be toggled between digit / segment waveform output.
(pins 9 - 24 can be used for the digit output)
parallel-drive available for large current VFD
• 16-step dimmer function available
(7) Timers
• Timer 0 : 16 bit timer / counter with capture register
Mode 0 : Two 8-bit timers with 8-bit programmable prescaler and 8-bit capture register
Mode 1 : 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with
8-bit capture register
Mode 2 : 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3 : 16-bit counter with 16-bit capture register
(8) Serial interface
• SIO 0 : 8 bit synchronous serial interface
1) LSB first / MSB first function available
2) An internal 8-bit baud-rate generator (maximum transmit clock period 4 / 3 tCYC)
3) Consecutive automatic data communication (1 - 256 bits)
• SIO 1 : 8 bit asynchronous / synchronous serial interface
Mode 0 : Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 tCYC)
Mode 1 : Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 – 2048 tCYC)
Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 tCYC)
Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection)
(9) AD converter
• 8 channels × 8-bit AD converter
(10) Remote receiver circuit (share with P15 / INT3 / T0IN terminal)
• Noise rejection function (The filtering time of the noise rejection filter (1 / 32 / 128 tCYC) can be switched by
program)
(11) Watchdog timer
• External RC circuit is required.
• Interrupt or system reset is activated when the timer overflows.
(12) System clock divider
• operable on the lowest power consumption
• Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be
switched by program (when using 10 MHz main clock)
No.7371-2/16
LC87F6032A
(13) Interrupts : 11-source and 9-vectored interrupt function
1) Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting.
During interrupt handling, an equal or lower level interrupt request is refused.
2) If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes
precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
2
3
4
5
6
7
8
9
Vector
00003H
0000BH
00013H
0001BH
00023H
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2 / T0L
INT3
T0H
SIO0
SIO1
ADC
VFD automatic display controller / Port 0
Interrupt signal
• Priority Level : X > H > L
• For equal priority levels, vector with lowest address takes precedence.
(14) Subroutine stack levels
• A maximum of 384 levels (set stack inside RAM)
(15) Multiplication and division
• 16 bits × 8 bits (5 instruction-cycle times)
• 24 bits × 16 bits (12 instruction-cycle times)
• 16 bits ÷ 8 bits (8 instruction-cycle times)
• 24 bits ÷ 16 bits (12 instruction-cycle times)
(16) Oscillation circuits
• Built-in RC oscillation circuit used for the system clock
• CF oscillation circuit used for the system clock. (Rf built in)
• Frequency-variable RC oscillation circuits for system clock use.
(17) Standby function
• HALT mode
The HALT mode stops program execution while the peripheral circuits keep operating and minimizes
power consumption. (VFD display and some serial transfer operations stop).
This operation mode can be released by a system reset or an interrupt request.
• HOLD mode
The HOLD mode stops program execution and CF and RC oscillation circuits.
This mode can be released by the following conditions.
(1) Supply "L" level to the reset terminal
(2) Supply the selected level to at least one of INT0, INT1, INT2
(3) Supply an interrupt condition to Port 0
(18) Shipping form
• QIP64E
(19) Development tools
• Evaluation (EVA) chip
• Emulator
: LC876093
: EVA62S + ECB876600 (Evaluation chip board) + SUB876000 + POD64QFP
: ICE-B877300 + SUB876000 + POD64QFP
(20) Same package and pin assignment as mask ROM version.
1) LC876000 series options can be set using flash ROM data.
Thus testing and evaluation of mass production boards is possible.
2) The flash version has the ability to emulate the RAM and ROM capacity of the mask ROM version.
No.7371-3/16
LC87F6032A
Pin Assignment
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
S30/PD6
S31/PD7
S32
S33
S34
S35
S36
S37
S38
S39
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
P06/AN6
2
P07/AN7
3
RES
4
VSS1
5
CF
6
CF2
7
VDD1
8
P70/INT0/T0LCP
9 10 11 12 13 14 15 16
P15/INT3/T0IN/SCK1
P11/SI0/SB0
P14/SI1/SB1
P16/INT1/T0HCP
P17/INT2/T0IN
P12/SCK0
P10/SO0
P13/SO1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
S0/T0
LC87F6032A
VP
Top view
SANYO : QIP64E
No.7371-4/16
LC87F6032A
System Block Diagram
Interrupt Control
IR
PLA
Standby Control
Flash ROM
MRC
RC
Clock
CF
Generator
PC
Bus Interface
ACC
SIO0
Port 0
B Register
SIO1
Port 1
C Register
Timer 0
ALU
Port 7
PSW
VFD Controller
ADC
RAR
INT0 - 3
Noise Rejection
RAM
Stack Pointer
WatchDog Timer
No.7371-5/16
stm32/stm8
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