3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK
TM
II PLUS
FEATURES:
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IDT5V996
3.3V operation
4 pairs of programmable skew outputs
Low skew: 150ps same pair, 350ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 25MHz to 225MHz
Output frequency: 25MHz to 225MHz
2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)
3-level inputs for skew control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <150ps peak-to-peak
Available in 144-pin BGA package
DESCRIPTION:
The IDT5V996 is a high fanout PLL based clock driver intended for high
performance computing and data-communication applications. The IDT5V996
has eight programmable skew outputs organized in four banks of two. Skew
is controlled by 3-level input signals that may be hard wired to appropriate
HIGH-MID-LOW levels. The IDT5V996 provides up to 18 programmable
levels of output skew, prescaling, and other features.
Other features of IDT5V996 are synchronous output enable (G), TEST,
and lock detect indicator (LOCK). When G is held low, all the outputs are
synchronously enabled, however, if G is held high, all outputs except 3Q0
and 3Q1 are in the state designated by SE (HIGH or LOW).
When TEST is held low, the chip operates in normal condition. When held
high, the PLL is shut off and the chip functions as a buffer. The lock detect
indicator asserts high when the phase lock loop has acquired lock. During
acquisition, the indicator is in the low state. Once the PLL has reached the
steady-state condition within a specified frequency range, LOCK is
asserted high.
The PLL is closed externally to provide more flexibility by allowing the
user to control the delay between the input clock and the outputs. The
IDT5V996 has LVTTL outputs with 12mA balanced drive outputs.
The IDT5V996 is characterized for operation from –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
G
Enable
Logic
SE
Skew
Select
3
3
3
1Q0
1Q 1
1F2:0
TEST
2Q0
Skew
Select
3
3
3
2Q1
REF
PLL
FB
Skew
Select
3
3
3
2F2:0
3Q 0
3Q1
LOCK
3F2:0
4Q0
Skew
Select
3
3
3
4Q 1
4F2:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2001
Integrated Device Technology, Inc.
DECEMBER 2001
DSC 5855/4
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
A
V
DDQ
V
DDQ
V
DDQ
GND
GND
LOCK
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
A
B
V
DDQ
V
DDQ
V
DDQ
GND
2Q1
2Q0
1Q1
1Q0
GND
V
DDQ
V
DDQ
V
DDQ
B
C
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
C
D
V
DDQ
V
DDQ
V
DD
GND
GND
GND
GND
GND
GND
V
DD
2F2
2F1
D
E
V
DDQ
G
V
DD
GND
GND
GND
GND
GND
GND
V
DD
2F0
1F2
E
F
TEST
REF
V
DD
GND
GND
GND
GND
GND
GND
V
DD
1F1
1F0
F
G
V
DDQ
FB
V
DD
GND
GND
GND
GND
GND
GND
V
DD
4F1
4F0
G
H
V
DDQ
SE
V
DD
GND
GND
GND
GND
GND
GND
V
DD
3F0
4F2
H
J
V
DDQ
V
DDQ
V
DD
GND
GND
GND
GND
GND
GND
V
DD
3F2
3F1
J
K
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
K
L
M
V
DDQ
V
DDQ
V
DDQ
GND
3Q1
3Q0
4Q1
4Q0
GND
V
DDQ
V
DDQ
V
DDQ
L
M
V
DDQ
V
DDQ
V
DDQ
GND
GND
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
BGA
TOP VIEW
2
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, V
DD
V
I
(2)
(2)
CAPACITANCE
(1,2)
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Unit
V
V
V
mA
mA
mA
°C
Parameter
C
IN
Description
Input Capacitance
V
I
= V
DDQ
or GND
NOTES:
1. Unused inputs must be held high or low to prevent them from floating.
2. Capacitance applies to all inputs except nF
2:0
. This value is characterized but not
production tested.
Description
Supply Voltage Range
Input Voltage Range
Voltage range applied to any
output in the high or low state
Input Clamp Current
Continuous Output Current
Continuous Current
Storage Temperature Range
Max
–0.5 to +4.6
–0.5 to 4.6
–0.5 to
V
DDQ
+ 0.5
–50
±50
±100
–65 to +150
Min
—
Typ.
8
Max.
—
Unit
pF
V
O
I
IK
(V
I
< 0)
I
O
(V
O
= 0 to V
DDQ
)
V
DDQ
or GND
T
STG
NOTES:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
PIN DESCRIPTION
Pin Name
REF
SE
Type
IN
IN
Description
Reference Clock Input
Selectable positive or negative edge control. When LOW / HIGH, the outputs are synchronized with the negative/positive edge of the
reference clock. When outputs are synchronously stopped with the G pin, SE determines the level at which outputs stop. When SE is
LOW/HIGH, outputs synchronously stop HIGH/LOW.
Feedback Input
Output gate for “true” nQ
[1:0]
outputs. When G is LOW, the “true” nQ
[1:0]
outputs are enabled. When G is HIGH, the “true” nQ
[1:0]
outputs
are in the state designated by SE (HIGH or LOW) (except 3Q
0
and 3Q
1
) - 3Q
0
and 3Q
1
may be used as the feedback signal to maintain
phase lock.
TEST = LOW means normal operation. TEST = HIGH means that the PLL is powered down and REF is routed to all the outputs. The
skews selected with the nF
[2:0]
pins are still in effect. (The TEST pin is a TTL input.)
nF[
2:0
]
nQ[
1:0
]
V
DDQ
V
DD
GND
LOCK
IN
OUT
PWR
PWR
PWR
OUT
3-level inputs for selecting 1 of 18 skew taps or frequency functions
Clock Output Pairs
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
Lock Detect. Asserted (HIGH) when the PLL is locked. The REF input must be oscillating.
FB
G
IN
IN
TEST
IN
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t
U
) which ranges
from 278ps to 625ps (see Programmable Skew Range and Resolution
Table). There are 16 skew configurations available for each output pair.
These configurations are chosen by the nF
2:0
control pins. In order to
3
minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
2:0
control pins.
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V996 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
Comments
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1)
Skew Adjustment Range
(2)
Max Adjustment:
±4.375ns
±157.5°
±43.75%
Example 1, F
NOM
= 100MHz
Example 2, F
NOM
= 167MHz
Example 3, F
NOM
= 225MHz
t
U
= 0.625ns
t
U
= 0.374ns
t
U
= 0.278ns
ns
Phase Degrees
% of Cycle Time
—
—
—
1/(16 x F
NOM
)
100 to 225 MHz
NOTES:
1. The VCO frequency always appears at nQ
1:0
outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be F
NOM
when
the output connected to FB is undivided. The frequency of the REF and FB inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for frequency multiplication by using
a divided output as the FB input. Using the nF[
2:0
] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals).
2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to all output pairs where ± 7t
U
skew adjustment is possible and at the lowest F
NOM
value.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
(1)
nF
2
L
L
L
L
M
M
M
M
M
M
M
M
M
H
H
H
H
H
H
nF
1
L
H
H
H
L
L
L
M
M
M
H
H
H
L
L
L
M
M
M
nF
0
L
L
M
H
L
M
H
L
M
H
L
M
H
L
M
H
L
M
H
Output Skew
Disable
(2)
-7t
U
-6t
U
-5t
U
-4t
U
-3t
U
-2t
U
-1t
U
Zero Skew
+1t
U
+2t
U
+3t
U
+4t
U
+5t
U
+6t
U
+7t
U
Inverted
Divide by 2
Divide by 4
NOTES:
1. All unused/unnoted combinations are reserved.
2. When G is LOW, all output pairs are individually disabled to the level designated by SE. When SE is LOW/HIGH, output pairs disable HIGH/LOW.
4
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
RECOMMENDED OPERATING RANGE
Symbol
V
DD
/ V
DDQ
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
3
-40
Typ.
3.3
+25
Max.
3.6
+85
Unit
V
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage Level
(1)
Input MID Voltage Level
(1)
Input LOW Voltage Level
(1)
Input Leakage Current
(REF, FB Inputs Only)
I
3
V
OH
V
OL
3-Level Input DC Current (nF
2:0
)
Output HIGH Voltage Level
Output LOW Voltage Level
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
CC
or GND
V
CC
= Max.
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
V
DD
= Min., I
OH
=
−
12mA
V
DD
= Min., I
OL
= 12mA
HIGH Level
MID Level
LOW Level
—
-50
-200
2.4
—
+200
+50
—
—
0.4
V
V
µA
Min.
2
—
V
DD
/2
−
0.3
—
-5
V
DD
−
0.6
Max.
—
0.8
—
V
DD
/2+0.3
0.6
+5
Unit
V
V
V
V
V
µA
NOTE:
1. These inputs are normally wired to V
DDQ
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
DDQ
/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional t
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