CMOS Static RAM
64K (64K x 1-Bit)
Description
IDT7187S
IDT7187L
x
Features
High speed (equal access and cycle time)
– Military: 25/35/45/55/70/85ns (max.)
Low power consumption
Battery backup operation—2V data retention
(L version only)
JEDEC standard high-density 22-pin ceramic
DIP packaging
Produced with advanced CMOS high-performance
technology
Separate data input and output
Input and output directly TTL-compatible
Military product compliant to MIL-STD-883, Class B
x
x
x
x
x
x
x
The IDT7187 is a 65,536-bit high-speed static RAM organized as 64K
x 1. It is fabricated using IDT’s high-performance, high-reliability CMOS
technology. Access times as fast as 25ns are available.
Both the standard (S) and low-power (L) versions of the IDT7187
provide two standby modes—I
SB
and I
SB1
. I
SB
provides low-power
operation; I
SB1
provides ultra-low-power operation. The low-power (L)
version also provides the capability for data retention using battery
backup. When using a 2V battery, the circuit typically consumes only
30µW.
Ease of system design is achieved by the IDT7187 with full
asynchronous operation, along with matching access and cycle times.
The device is packaged in an industry standard 22-pin, 300 mil ceramic
DIP.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
Functional Block Diagram
A
A
V
CC
A
A
A
A
A
CS
DATA
IN
COLUMN I/O
DATA
OUT
ROW
SELECT
65,536-BIT
MEMORY ARRAY
GND
WE
A
A
A
A
A
A
A
2986 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-2986/09
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Pin Configuration
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
DATA
OUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
Absolute Maximum Ratings
(1)
Symbol
Rating
Terminal Voltage with Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7.0
-55 to +125
-65 to +135
-65 to +150
1.0
50
Unit
V
o
o
o
D22-1
V
CC
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
DATA
IN
CS
2986 drw 02
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
,
C
C
C
W
mA
2986 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
DIP
Top View
Capacitance
(T
A
= +25°C, f = 1.0MH
z
)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
2986 tbl 04
Pin Descriptions
Name
A
0
- A
15
CS
WE
V
CC
DATA
IN
DATA
OUT
GND
Description
Address Inputs
Chip Select
Write Enable
Power
Data Input
Data Output
Ground
2986 tbl 01
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Recommended DC Operations
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
2986 tbl 05
____
Truth Table
(1)
Mode
Standby
Read
Write
CS
H
L
L
WE
X
H
L
Output
High-Z
D
OUT
High-Z
Power
Standby
Active
Active
2986 tbl 02
NOTE:
1. V
IL
(min.) = –3.0V for pulse width less than 20ns, once per cycle.
Recommended Operating
Temperature and Supply Voltage
Grade
Military
Temperature
-55
O
C to +125
O
C
GND
0V
Vcc
5V ± 10%
2986 tbl 06
NOTE:
1. H = V
IH
, L = V
IL
, X = don't care.
2
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
IDT7187S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
V
CC
= Max., V
IN =
GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 10mA, V
CC
= Min.
I
OL
= 8mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
Min.
____
IDT7187L
Min.
____
Max.
10
10
0.5
0.4
____
Max.
5
5
0.5
0.4
____
Unit
µA
µA
V
____
____
____
____
____
____
2.4
2.4
V
2986 tbl 07
DC Electrical Characteristics
(1)
Symbol
I
CC1
Parameter
Operating Power
Supply Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f
=
0
(2)
Dynamic Operating Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
Standby Power Supply
Current (TTL Level)
CS
> V
IH
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
Full Standby Power
Supply Current (CMOS Level)
CS
> V
HC
, V
CC
= Max., V
IN
< V
LC
or V
IN
> V
HC
, f = 0
(2)
Power
S
L
S
L
S
L
S
L
(V
CC
= 5V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
7187S25
7187L25
105
85
130
110
55
50
20
1.5
7187S35
7187L35
105
85
120
100
50
40
20
1.5
7187S45
7187L45
105
85
120
95
50
35
20
1.5
7187S55
7187L55
105
85
120
90
50
30
20
1.5
7187S70
7187L70
105
85
120
90
50
28
20
1.5
7187S85
7187L85
105
85
120
90
50
28
20
1.5
2986 tbl 08
Unit
mA
I
CC2
mA
I
SB
mA
I
SB1
mA
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX
address and data inputs are cycling at the maximum frequency of read cycles of 1/t
RC
. f = 0 means no input lines change.
6.42
3
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Data Retention Characteristics
(L Version Only) (V
HC
= V
CC
- 0.2V, V
LC
= 0.2V)
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR
(3)
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Tim
Operation Recovery Time
Input Leakage Current
CS
> V
HC
V
IN
> V
HC
or <
V
LC
Test Condition
____
Max.
V
CC
@
3.0V
____
Min.
2.0
____
2.0V
____
2.0V
____
3.0V
____
Unit
V
µA
ns
ns
µA
2986 tbl 09
10
____
15
____
600
____
900
____
0
t
RC
(2)
____
____
____
____
____
I
I
LI
I
(3)
____
____
2
2
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed, but not tested.
Low V
CC
Data Retention Waveform
DATA
RETENTION
MODE
V
CC
4.5V
t
CDR
CS
V
IH
V
DR
≥
2V
V
IH
2986 drw 04
4.5V
t
R
V
DR
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2986 tbl 10
5V
480Ω
DATA
OUT
255Ω
30pF*
,
5V
480Ω
DATA
OUT
255Ω
5pF*
,
2986 drw 06
2986 drw 05
Figure 1. AC Test Load
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for t
HZ
, t
LZ
, t
WZ
and t
OW
)
4
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
7187S25
7187L25
Symbol
Parameter
Min.
Max.
7187S35/45
7187L35/45
Min.
Max.
7187S55
7187L55
Min.
Max.
7187S70
7187L70
Min.
Max.
7187S85
7187L85
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
OH
t
LZ
(1)
t
HZ
(1)
t
PU
(1)
t
PD
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Output Select to Output in Low-Z
Chip Deselect to Output in High-Z
Chip Select to Power Up Time
Chip Deselect to Power Down Time
25
____
____
35/45
____
____
55
____
____
70
____
____
85
____
____
ns
ns
ns
ns
ns
ns
ns
ns
2986 tbl 11
25
25
____
35/45
35/45
____
55
55
____
70
70
____
85
85
____
____
____
____
____
____
5
5
____
5
5
____
5
5
____
5
5
____
5
5
____
____
____
____
____
____
12
____
17/20
____
30
____
30
____
40
____
0
____
0
____
0
____
0
____
0
____
20
30/35
35
35
40
NOTE:
1. This parameter guaranteed but not tested.
Timing Waveform of Read Cycle No. 1
(1,2)
t
RC (5)
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
2986 drw 07
Timing Waveform of Read Cycle No. 2
(1,3)
t
RC (5)
CS
t
ACS
t
LZ (4)
DATA
OUT
t
PU
V
CC
SUPPLY
CURRENT
I
CC
I
SB
2986 drw 08
t
HZ(4)
DATA VALID
t
PD
HIGH
IMPEDANCE
NOTES:
1.
WE
is HIGH for Read cycle.
2.
CS
is LOW for Read cycle.
3. Address valid prior to or coincident with
CS
transition LOW.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.42
5
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