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MC74AC299, MC74ACT299
8−Input Universal Shift/
Storage Register with
Common Parallel I/O Pins
The MC74AC299/74ACT299 is an 8−bit universal shift/storage
register with 3−state outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel load inputs
and flip−flop outputs are multiplexed to reduce the total number of
package pins. Additional outputs are provided for flip−flops Q
0
, Q
7
to
allow easy serial cascading. A separate active LOW Master Reset is
used to reset the register.
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•
•
•
•
•
•
w
PDIP−20
N SUFFIX
CASE 738
20
1
Common Parallel I/O for Reduced Pin Count
Additional Serial Inputs and Outputs for Expansion
Four Operating Modes: Shift Left, Shift Right, Load and Store
3−State Outputs for Bus−Oriented Applications
Outputs Source/Sink 24 mA
′ACT299
Has TTL Compatible Inputs
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
V
CC
20
S
1
19
DS
7
18
Q
7
17
I/O
7
16
I/O
5
15
I/O
3
14
I/O
1
13
CP
12
DS
0
11
20
1
SO−20
DW SUFFIX
CASE 751
ORDERING INFORMATION
Device
MC74AC299N
MC74ACT299N
MC74AC299DW
MC74AC299DWR2
MC74ACT299DW
Package
PDIP−20
PDIP−20
SOIC−20
SOIC−20
SOIC−20
SOIC−20
Shipping
18 Units/Rail
18 Units/Rail
38 Units/Rail
1000 Tape & Reel
38 Units/Rail
1000 Tape & Reel
1
S
0
2
OE
1
3
OE
2
4
I/O
6
5
I/O
4
6
I/O
2
7
I/O
0
8
Q
0
9
MR
10
GND
MC74ACT299DWR2
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
PIN ASSIGNMENT
PIN
CP
DS
0
DS
7
S
0
, S
1
MR
OE
1
, OE
2
I/O
0
−I/O
7
Q
0
, Q
7
FUNCTION
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
3−State Output Enable Inputs
Parallel Data Inputs or 3−State Parallel Outputs
Serial Outputs
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 8
1
Publication Order Number:
MC74AC299/D
MC74AC299, MC74ACT299
DS
7
Q
7
S
0
S
1
CP
DS
0
DS
7
Q
7
D Q
C
D
I/O
7
OE MR Q I/O I/O I/O I/O I/O I/O I/O I/O
0
0
1
2
3
4
5
6
7
CP
Figure 2. Logic Symbol
D Q
C
D
I/O
6
CP
D Q
C
D
I/O
5
CP
D Q
C
D
I/O
4
CP
D Q
C
D
I/O
3
CP
D Q
C
D
I/O
2
CP
D Q
C
D
I/O
1
CP
D Q
C
D
S
0
I/O
0
S
1
DS
0
CP
OE
1
Q
0
MR
OE
2
NOTE:
That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
MC74AC299, MC74ACT299
FUNCTIONAL DESCRIPTION
The MC74AC299/74ACT299 contains eight edge−triggered
D−type flip−flops and the interstage logic necessary to
perform synchronous shift left, shift right, parallel load and
hold operations. The type of operation is determined by S
0
and S
1
, as shown in the Truth Table. All flip−flop outputs are
brought out through 3−state buffers to separate I/O pins that
also serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip−flops. All other state changes are initiated
by the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
A HIGH signal on either OE
1
or OE
2
disables the 3
-
state
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can
still occur. The 3−state buffers are also disabled by HIGH
signals on both S
0
and S
1
in preparation for a parallel load
operation.
TRUTH TABLE
Inputs
MR
L
H
H
H
H
S
1
X
H
L
H
L
S
0
X
H
H
L
L
CP
X
Response
Asynchronous Reset; Q
0
−Q
7
= LOW
Parallel Load; I/O
n
→
Q
n
Shift Rights; DS
0
→
Q
0
, Q
0
→
Q
1
, etc.
Shift Left; DS
7
→
Q
7
, Q
7
→
Q
6
, etc.
Hold
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
MAXIMUM RATINGS*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
T
stg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V
CC
or GND Current per Output Pin
Storage Temperature
Value
−0.5
to +7.0
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
±20
±50
±50
−65
to +150
Unit
V
V
V
mA
mA
mA
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
t
r
, t
f
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current
−
High
Output Current
−
Low
V
CC
@ 3.0 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−
−40
−
−
Typ
5.0
5.0
−
150
40
25
10
8.0
−
25
−
−
Max
6.0
5.5
V
CC
−
−
−
−
−
140
85
−24
24
ns/V
°C
°C
mA
mA
ns/V
Unit
V
V
t
r
, t
f
T
J
T
A
I
OH
I
OL
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC299, MC74ACT299
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OZT
Maximum Input
Leakage Current
Maximum 3−State
Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
74AC
T
A
=
−40°C
to
+85°C
Unit
Conditions
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
I
OUT
=
−50
μA
V
IL
V
V
OH
V
V
*V
IN
= V
IL
or V
IH
−12
mA
I
OH
−24
mA
−24
mA
I
OUT
= 50
μA
V
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
I
(OE) = V
IL
, V
IH
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
μA
5.5
5.5
5.5
5.5
−
−
−
−
±0.6
−
−
8.0
±6.0
75
−75
80
μA
mA
mA
μA
I
OLD
I
OHD
I
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
AC CHARACTERISTICS
(For Figures and Waveforms
−
See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
Symbol
Parameter
V
CC
*
(V)
Min
f
max
t
PLH
t
PHL
Maximum Input
Frequency
Propagation Delay
CP to Q
0 or
Q
7
Propagation Delay
CP to Q
0 or
Q
7
3.3
5.0
3.3
5.0
3.3
5.0
90
130
8.5
5.5
8.5
5.5
T
A
= +25°C
C
L
= 50 pF
Typ
−
−
−
−
−
−
Max
−
−
20.5
14
21.5
14.5
74AC
T
A
=
−40°C
to +85°C
C
L
= 50 pF
Min
80
105
7.0
4.5
7.0
5.0
Max
−
−
22
15
23
16
MHz
ns
ns
3−3
3−6
3−6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
Voltage Range 5.0 V is 5.0 V
±0.5
V.
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4
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