MJD128T4G,
NJVMJD128T4G (PNP)
Complementary Darlington
Power Transistor
DPAK For Surface Mount Applications
Designed for general purpose amplifier and low speed switching
applications.
Features
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Monolithic Construction With Built−in Base−Emitter Shunt Resistors
High DC Current Gain: h
FE
= 2500 (Typ) @ I
C
= 4.0 Adc
Epoxy Meets UL 94 V−0 @ 0.125 in.
ESD Ratings:
Human Body Model, 3B > 8000 V
Machine Model, C > 400 V
NJV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These are Pb−Free Devices*
SILICON
POWER TRANSISTOR
8 AMPERES
120 VOLTS, 20 WATTS
DPAK
CASE 369C
STYLE 1
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MAXIMUM RATINGS
Rating
Symbol
V
CEO
V
CB
V
EB
I
C
Value
120
120
5
8
16
120
20
0.16
1.75
0.014
−65
to
+ 150
Unit
Vdc
Vdc
Vdc
Adc
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
Collector Current
Continuous
Peak
Base Current
Total Power Dissipation
@ T
C
= 25C
Derate above 25C
Total Power Dissipation*
@ T
A
= 25C
Derate above 25C
Operating and Storage Junction
Temperature Range
I
B
P
D
mAdc
W
W/C
W
W/C
C
P
D
T
J
, T
stg
MARKING DIAGRAM
Base
Collector
Emitter
A
Y
WW
J128
G
3
= Assembly Location
= Year
= Work Week
= Device Code
= Pb−Free Package
1
2
AYWW
J128G
4
ORDERING INFORMATION
Device
MJD128T4G
NJVMJD128T4G
Package
DPAK
(Pb−Free)
DPAK
(Pb−Free)
Shipping
†
2,500/Tape & Reel
2,500/Tape & Reel
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THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance,
Symbol
R
qJC
R
qJA
Max
Unit
Junction−to−Case
6.25
71.4
C/W
C/W
Thermal Resistance,
Junction−to−Ambient (Note 1)
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2012
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
February, 2012
−
Rev. 5
1
Publication Order Number:
MJD128/D
MJD128T4G, NJVMJD128T4G (PNP)
PD, POWER DISSIPATION (WATTS)
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ELECTRICAL CHARACTERISTICS
(T
C
= 25C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage
(I
C
= 30 mAdc, I
B
= 0)
V
CEO(sus)
I
CEO
I
CBO
I
EBO
120
−
Vdc
Collector Cutoff Current
(V
CE
= 120 Vdc, I
B
= 0)
Collector Cutoff Current
(V
CB
= 100 Vdc, I
E
= 0)
Emitter Cutoff Current
(V
BE
= 5 Vdc, I
C
= 0)
ON CHARACTERISTICS
DC Current Gain
(I
C
= 4 Adc, V
CE
= 4 Vdc)
(I
C
= 8 Adc, V
CE
= 4 Vdc)
Collector−Emitter Saturation Voltage
(I
C
= 4 Adc, I
B
= 16 mAdc)
(I
C
= 8 Adc, I
B
= 80 mAdc)
Base−Emitter Saturation Voltage (1)
(I
C
= 8 Adc, I
B
= 80 mAdc)
Base−Emitter On Voltage
(I
C
= 4 Adc, V
CE
= 4 Vdc)
DYNAMIC CHARACTERISTICS
Current−Gain−Bandwidth Product
(I
C
= 3 Adc, V
CE
= 4 Vdc, f = 1 MHz)
Output Capacitance
(V
CB
= 10 Vdc, I
E
= 0, f = 0.1 MHz)
Small−Signal Current Gain
(I
C
= 3 Adc, V
CE
= 4 Vdc, f = 1 kHz)
2. Pulse Test: Pulse Width
v
300
ms,
Duty Cycle
v
2%.
T
A
T
C
2.5 25
|h
fe
|
C
ob
4
−
MHz
h
FE
−
1000
100
12,000
−
Vdc
−
−
2
4
Vdc
−
5
mA
−
10
mAdc
−
2
mAdc
V
CE(sat)
V
BE(sat)
V
BE(on)
−
4.5
−
2.8
Vdc
−
300
pF
h
fe
300
−
−
2 20
T
C
T
A
SURFACE
MOUNT
1.5 15
1 10
0.5
5
0
0
25
50
75
100
T, TEMPERATURE (C)
125
150
Figure 1. Power Derating
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2
MJD128T4G, NJVMJD128T4G (PNP)
TYPICAL ELECTRICAL CHARACTERISTICS
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
20,000
V
CE
= 4 V
hFE, DC CURRENT GAIN
10,000
7000
5000
3000
2000
25C
1000
700
500
300
200
0.1
- 55C
3
T
J
= 25C
2.6
I
C
= 2 A
4A
6A
T
J
= 150C
2.2
1.8
1.4
1
0.3
0.2
0.3
0.5 0.7
1
2
3
5
7
10
0.5 0.7
1
2
3
5
7
10
20
30
I
C
, COLLECTOR CURRENT (AMP)
I
B
, BASE CURRENT (mA)
Figure 2. DC Current Gain
V, TEMPERATURE COEFFICIENTS (mV/
C)
3
T
J
= 25C
V, VOLTAGE (VOLTS)
2.5
+5
+4
+3
+2
+1
0
-1
-2
-3
-4
-5
0.1
Figure 3. Collector Saturation Region
*I
C
/I
B
h
FE/3
2
25C to 150C
q
VC
for V
CE(sat)
- 55C to 25C
25C to 150C
1.5
V
BE
@ V
CE
= 4 V
V
BE(sat)
@ I
C
/I
B
= 250
V
CE(sat)
@ I
C
/I
B
= 250
1
0.5
0.1
q
VB
for V
BE
- 55C to 25C
0.2 0.3
0.5 0.7
1
2
3
5
7
10
I
C
, COLLECTOR CURRENT (AMP)
1
2 3
0.5
0.2 0.3
I
C
, COLLECTOR CURRENT (AMP)
5
7
10
Figure 4. “On” Voltages
IC
, COLLECTOR CURRENT ( A)
10
5
REVERSE
10
4
10
3
10
2
10
1
10
0
T
J
= 150C
100C
25C
V
CE
= 30 V
FORWARD
hfe
, SMALL−SIGNAL CURRENT GAIN
10,000
5000
3000
2000
1000
500
300
200
100
50
30
20
10
1
2
Figure 5. Temperature Coefficients
T
C
= 25C
V
CE
= 4 Vdc
I
C
= 3 Adc
PNP
NPN
5
10
20
50 100
f, FREQUENCY (kHz)
200
500 1000
10
-1
+ 0.6 + 0.4 + 0.2
0 - 0.2 - 0.4 - 0.6 - 0.8 - 1 - 1.2 - 1.4
V
BE
, BASE−EMITTER VOLTAGE (VOLTS)
Figure 6. Collector Cut−Off Region
Figure 7. Small−Signal Current Gain
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3
MJD128T4G, NJVMJD128T4G (PNP)
300
T
J
= 25C
200
C, CAPACITANCE (pF)
C
ob
100
70
C
ib
50
30
0.1
0.2
0.5
1
2
5
10
20
50
100
V
R
, REVERSE VOLTAGE (VOLTS)
Figure 8. Capacitance
5
R
B
& R
C
VARIED TO OBTAIN DESIRED CURRENT LEVELS
D
1
, MUST BE FAST RECOVERY TYPE, e.g.:
1N5825 USED ABOVE I
B
100 mA
MSD6100 USED BELOW I
B
100 mA
TUT
V
2
APPROX
+8 V
0
V
1
APPROX
-12 V
t
r
, t
f
10 ns
DUTY CYCLE = 1%
R
B
51
D
1
+4V
8 k
120
V
CC
- 30 V
R
C
SCOPE
t, TIME (
s)
3
2
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.1
t
s
t
f
25
ms
FOR t
d
AND t
r
, D
1
IS DISCONNECTED
AND V
2
= 0
FOR NPN TEST CIRCUIT REVERSE ALL POLARITIES.
V
CC
= 30 V
I
C
/I
B
= 250
I
B1
= I
B2
T
J
= 25C
0.2
t
r
t
d
@ V
BE(off)
= 0 V
5
7
10
0.3
0.5 0.7 1
3
2
I
C
, COLLECTOR CURRENT (AMP)
Figure 9. Switching Times Test Circuit
Figure 10. Switching Times
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.01
D = 0.5
0.2
0.1
0.05
0.01
SINGLE PULSE
P
(pk)
R
qJC(t)
= r(t) R
qJC
R
qJC
= 6.25C/W
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
1
READ TIME AT t
1
t
2
T
J(pk)
−
T
C
= P
(pk)
q
JC(t)
DUTY CYCLE, D = t
1
/t
2
0.1
0.2 0.3
0.5
1
2
3
5
10
t, TIME OR PULSE WIDTH (ms)
20
30
50
100
200 300
500
1000
0.02 0.03
0.05
Figure 11. Thermal Response
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4
MJD128T4G, NJVMJD128T4G (PNP)
20
15
10
5
3
2
1
0.5
0.3
0.2
0.1
T
J
= 150C
1 ms
5 ms
BONDING WIRE LIMIT
THERMAL LIMIT
T
C
= 25C (SINGLE PULSE)
SECOND BREAKDOWN LIMIT
CURVES APPLY BELOW RATED V
CEO
1
2
3
5
7
10
20
30
50
IC, COLLECTOR CURRENT (AMP)
500
ms
100
ms
dc
0.05
0.03
0.02
100 120 200
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
−
V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 12 is based on T
J(pk)
= 150C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
< 150C. T
J(pk)
may be calculated from the data in
Figure 11. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 12. Maximum Forward Bias
Safe Operating REA
COLLECTOR
BASE
8k
120
EMITTER
Figure 13. Darlington Schematic
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