SN74LS90
DECADE COUNTER;
DIVIDE-BY-TWELVE
COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are
high-speed 4-bit ripple type counters partitioned into two sections.
Each counter has a divide-by-two section and either a divide-by-five
(LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which
are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP) to form BCD,
bi-quinary, modulo-12, or modulo-16 counters. All of the counters
have a 2-input gated Master Reset (Clear), and the LS90 also has a
2-input gated Master Set (Preset 9).
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DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
•
Low Power Consumption . . . Typically 45 mW
•
High Count Rates . . . Typically 42 MHz
•
Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
•
Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
14
1
J SUFFIX
CERAMIC
CASE 632-08
LOADING
(Note a)
HIGH
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
14
1
CP
0
CP
1
CP
1
MR
1
, MR
2
MS
1
, MS
2
Q
0
Q
1
, Q
2
, Q
3
Clock (Active LOW going edge) Input to
÷2
Section
Clock (Active LOW going edge) Input to
÷5
Section (LS90),
÷6
Section (LS92)
Clock (Active LOW going edge) Input to
÷8
Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from
÷2
Section (Notes b & c)
Outputs from
÷5
(LS90),
÷6
(LS92),
÷8
(LS93) Sections (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
μA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b.
Temperature Ranges.
c. The Q
0
Outputs are guaranteed to drive the full fan-out plus the CP
1
input of the device.
d. To insure proper operation the rise (t
r
) and fall time (t
f
) of the clock must be less than 100 ns.
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
6 7
1 2
14
1
MS
CP
0
CP
1
MR Q
0
Q
1
Q
2
Q
3
1 2
2 3 12 9 8 11
V
CC
= PIN 5
GND = PIN 10
NC = PINS 4, 13
©
Semiconductor Components Industries, LLC, 2006
LOGIC SYMBOL
LS90
14
1
CP
0
CP
1
MR Q
0
Q
1
Q
2
Q
3
1 2
6 7 12 11 9 8
V
CC
= PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
1
LS92
14
1
CP
0
LS93
CP
1
MR Q
0
Q
1
Q
2
Q
3
1 2
2 3 12 9 8 11
V
CC
= PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
Publication Order Number:
SN74LS90/D
July, 2006
−
Rev. 6
SN74LS90
LOGIC DIAGRAM
MS
1
MS
2
6
7
CONNECTION DIAGRAM
LS90
DIP
(TOP VIEW)
CP
1
1
14 CP
0
13 NC
12 Q
0
11 Q
3
10 GND
9 Q
1
8 Q
2
CP
0
14
J
S
D
Q
J
S
D
Q
J
S
D
Q
R
S
D
Q
MR
1
2
MR
2
3
NC 4
V
CC
5
MS
1
6
MS
2
7
Q
3
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
CP
SC Q
D
CP
1
MR
1
MR
2
1
2
3
Q
0
12
Q
1
9
Q
2
8
11
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
= PIN NUMBERS
V
CC
= PIN 5
GND = PIN 10
LOGIC DIAGRAM
LS92
CONNECTION DIAGRAM
DIP
(TOP VIEW)
CP
1
1
14 CP
0
13 NC
12 Q
0
11 Q
1
10 GND
9 Q
2
8 Q
3
CP
0
14
J
Q
J
Q
J
Q
J
Q
NC 2
NC 3
NC 4
V
CC
5
MR
1
6
MR
2
7
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
CP
1
MR
1
MR
2
1
6
12
7
11
9
8
Q
0
Q
1
Q
2
Q
3
= PIN NUMBERS
V
CC
= PIN 5
GND = PIN 10
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
LOGIC DIAGRAM
LS93
J
Q
J
Q
J
Q
J
Q
CONNECTION DIAGRAM
DIP
(TOP VIEW)
CP
1
1
14 CP
0
13 NC
12 Q
0
11 Q
3
10 GND
9 Q
1
8 Q
2
CP
0
14
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
MR
1
2
MR
2
3
NC 4
V
CC
5
CP
1
MR
1
MR
2
1
2
12
3
9
8
11
NC 6
Q
3
NC 7
Q
0
Q
1
Q
2
= PIN NUMBERS
V
CC
= PIN 5
GND = PIN 10
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
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2
SN74LS90
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade,
Divide-By-Twelve, and Binary Counters respectively. Each
device consists of four master/slave flip-flops which are
internally connected to provide a divide-by-two section and a
divide-by-five
(LS90),
divide-by-six
(LS92),
or
divide-by-eight (LS93) section. Each section has a separate
clock input which initiates state changes of the counter on the
HIGH-to-LOW clock transition. State changes of the Q
outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject
to decoding spikes and should not be used for clocks or
strobes. The Q
0
output of each device is designed and
specified to drive the rated fan-out plus the CP
1
input of the
device.
A gated AND asynchronous Master Reset (MR
1
•
MR
2
) is
provided on all counters which overrides and clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS
1
•
MS
2
) is provided on the LS90 which
overrides the clocks and the MR inputs and sets the outputs
to nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes.
LS90
A. BCD Decade (8421) Counter — The CP
1
input must be
externally connected to the Q
0
output. The CP
0
input
receives the incoming count and a BCD count sequence
is produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q
3
output must be externally connected to the CP
0
input. The
input count is then applied to the CP
1
input and a
divide-by-ten square wave is obtained at output Q
0
.
C. Divide-By-Two and Divide-By-Five Counter — No
external interconnections are required. The first flip-flop is
used as a binary element for the divide-by-two function
(CP
0
as the input and Q
0
as the output). The CP
1
input is
used to obtain binary divide-by-five operation at the Q
3
output.
LS92
A. Modulo 12, Divide-By-Twelve Counter — The CP
1
input
must be externally connected to the Q
0
output. The CP
0
input receives the incoming count and Q
3
produces a
symmetrical divide-by-twelve square wave output.
B. Divide-By-Two and Divide-By-Six Counter —No external
interconnections are required. The first flip-flop is used as
a binary element for the divide-by-two function. The CP
1
input is used to obtain divide-by-three operation at the Q
1
and Q
2
outputs and divide-by-six operation at the Q
3
output.
LS93
A. 4-Bit Ripple Counter — The output Q
0
must be externally
connected to input CP
1
. The input count pulses are
applied to input CP
0
. Simultaneous divisions of 2, 4, 8,
and 16 are performed at the Q
0
, Q
1
, Q
2
, and Q
3
outputs as
shown in the truth table.
B. 3-Bit Ripple Counter— The input count pulses are applied
to input CP
1
. Simultaneous frequency divisions of 2, 4,
and 8 are available at the Q
1
, Q
2
, and Q
3
outputs.
Independent use of the first flip-flop is available if the reset
function coincides with reset of the 3-bit ripple-through
counter.
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