N01L6183A
1Mb Ultra-Low Power Asynchronous CMOS SRAM
64K × 16 bit
Overview
The N01L6183A is an integrated memory device
containing a 1 Mbit Static Random Access Memory
organized as 65,536 words by 16 bits. The device
is designed and fabricated using ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with a single chip
enable (CE) control and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently. The N01L6183A is
optimal for various applications where low-power is
critical such as battery backup and hand-held
devices. The device can operate over a very wide
temperature range of -40
o
C to +85
o
C and is
available in JEDEC standard packages compatible
with other standard 64Kb x 16 SRAMs.
Features
• Single Wide Power Supply Range
1.65 to 2.2 Volts
• Very low standby current
0.5µA at 1.8V (Typical)
• Very low operating current
0.7mA at 1.8V and 1µs (Typical)
• Very low Page Mode operating current
0.5mA at 1.8V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.2V
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Product Family
Part Number
N01L6183AB
N01L6183AT
N01L6183AB2
N01L6183AT2
Package Type
48 - BGA
44 - TSOP II
48 - BGA Green
44 - TSOP II Green
70ns @ 1.8V
-40
o
C to +85
o
C 1.65V - 2.2V 85ns @ 1.65V
0.5
µA
0.7 mA @
1MHz
Operating
Power
Temperature Supply (Vcc)
Speed
Standby
Operating
Current (I
SB
), Current (Icc),
Typical
Typical
Pin Configurations
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
VCC
VSS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN
ONE
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
I/O
15
I/O
14
I/O
13
I/O
12
VSS
VCC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
1
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
V
SS
V
CC
2
OE
UB
I/O
10
I/O
11
I/O
12
3
A
0
A
3
A
5
NC
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
NC
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
Pin Descriptions
Pin Name
A
0
-A
15
WE
CE
OE
LB
UB
I/O
0
-I/O
15
NC
V
CC
V
SS
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Not Connected
Power
Ground
N01L6183A
TSOP
I/O
14
I/O
13
I/O
15
NC
NC
A
8
48 Pin BGA (top)
6 x 8 mm
©2008 SCILLC. All rights reserved.
July 2008 - Rev.
8
Publication Order Number:
N01L6183A/D
N01L6183A
Functional Block Diagram
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A15
Page
Address
Decode
Logic
4K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
Word Mux
I/O0 - I/O7
I/O8 - I/O15
CE
WE
OE
UB
LB
Control
Logic
Functional Description
CE
H
L
L
L
L
WE
X
X
L
H
H
OE
X
X
X
3
L
H
UB
X
H
L
1
L
1
L
1
LB
X
H
L
1
L
1
L
1
I/O
0
- I/O
151
High Z
High Z
Data In
Data Out
High Z
MODE
Standby
2
Active
Write
3
Read
Active
POWER
Standby
Active
Active -> Standby
4
Active -> Standby
4
Standby
4
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any
external influence.
Capacitance
1
Item
Input Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
Min
Max
8
8
Unit
pF
pF
1. These parameters are verified in device characterization and are not 100% tested
Rev.
8
| Page 2 of 10 | www.onsemi.com
N01L6183A
Absolute Maximum Ratings
1
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Soldering Temperature and Time
Symbol
V
IN,OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
Rating
–0.3 to V
CC
+0.3
–0.3 to 3.0
500
–40 to 125
-40 to +85
260
o
C, 10sec
Unit
V
V
mW
o
C
o
C
o
C
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item
Supply Voltage
Data Retention Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Read/Write Operating Supply Current
@ 1
µs
Cycle Time
2
Read/Write Operating Supply Current
@ 85 ns Cycle Time
2
Page Mode Operating Supply Current
@ 85ns Cycle Time
2
(Refer to Power
Savings with Page Mode Operation
diagram)
Read/Write Quiescent Operating Sup-
ply Current
3
Symbol
V
CC
V
DR
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
OH
= 0.2mA
I
OL
= -0.2mA
V
IN
= 0 to V
CC
OE = V
IH
or Chip Disabled
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
f=0
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 2.2 V
V
CC
= 1.2V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
0.5
0.7
8
Chip Disabled
3
Test Conditions
Min.
1.65
1.2
0.7V
CC
–0.3
V
CC
–0.3
0.3
0.5
0.5
3.0
16
V
CC
+0.3
0.3V
CC
Typ
1
1.8
Max
2.2
Unit
V
V
V
V
V
V
µA
µA
mA
mA
I
CC3
3
mA
I
CC4
20
µA
Maximum Standby Current
3
I
SB1
10
µA
Maximum Data Retention Current
3
I
DR
5
µA
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25°C and are not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
Rev.
8
| Page 3 of 10 | www.onsemi.com
N01L6183A
Power Savings with Page Mode Operation (WE
=
V
IH
)
Page Address (A4 - A15 )
Open page
...
Word Address (A0 - A3)
Word 1
Word 2
Word 16
CE
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Rev.
8
| Page 4 of 10 | www.onsemi.com
N01L6183A
Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature
0.1V
CC
to 0.9 V
CC
5ns
0.5 V
CC
CL = 30pF
-40 to +85
o
C
Timing
Item
Read Cycle Time
Address Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Address Setup Time
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
Symbol
t
RC
t
AA
t
CO
t
OE
t
LB
, t
UB
t
LZ
t
OLZ
t
LBZ
, t
UBZ
t
HZ
t
OHZ
t
LBHZ
, t
UBHZ
t
OH
t
WC
t
CW
t
AW
t
LBW
, t
UBW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
40
0
10
5
85
50
50
50
50
0
0
25
35
0
10
10
5
10
30
30
30
5
70
40
40
40
40
0
0
20
1.65 - 2.2 V
Min.
85
85
85
35
30
10
5
10
25
25
25
Max.
1.8 - 2.2 V
Min.
70
70
70
30
25
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.
8
| Page 5 of 10 | www.onsemi.com
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