CBTL12131
DisplayPort multiplexer for bidirectional video in all-in-one
computer systems
Rev. 1 — 25 February 2011
Product data sheet
1. General description
CBTL12131 is an integrated DisplayPort high-speed path switch/multiplexer that allows
all-in-one computer systems to efficiently manage path switching between different
display modes of operation. With the CBTL12131, video can be routed either from one
DisplayPort source (GPU1) to an integrated DisplayPort panel and simultaneously from a
second DisplayPort source (GPU2) to an external DisplayPort sink; or from an external
DisplayPort source to the integrated DisplayPort panel.
The device is configured as four main Ports A through D, each providing four high-speed
differential lanes for DisplayPort Main Link (ML) channels, one high-speed differential lane
for the DisplayPort AUX channel, and one single-ended lane for the HPD (Hot Plug
Detect) signal. One port (Port A) provides an additional alternate lane for the AUX
channel, in order to allow bypassing of external AC-coupling capacitors for support of the
DDC channel in case an external connected sink is a ‘++DP’ type cable adapter.
For the path supporting the ‘external source to integrated DisplayPort panel’ mode, a
programmable equalizer is provided which allows compensation for channel loss that the
external source or internal sink are unable to adequately compensate for. The equalizer is
self-biasing and is programmable to five gain-frequency curves, of which one is a flat
response and four are active equalization. The equalizer output can also be set to one of
two levels of pre-emphasis (including flat), and also differential swing level can be set to
one of two levels. All options (EQ, pre-emphasis, level) are easily programmed using
board-strapping (resistor, short or open) of three unique Quinary Input programming pins.
The CBTL12131 includes additional features that support use of the external DisplayPort
connector in both directions: either an external sink (monitor or cable adapter) or external
source (notebook computer) can be connected, while CBTL12131 configures the direction
and termination of the related signals accordingly. The port facing the external DisplayPort
connector (Port B) is equipped with dedicated sensing circuitry which detects and reports
the status of the HPD and AUX lines, to support the system controller in determining and
setting the proper connection status. The AUX channel of Port B also has switchable
integrated termination, to allow the system controller to apply the correct DC termination
in case an external DisplayPort source is connected. Moreover, it affords the system
controller the means to detect the type of system (sink, source or all-in-one computer)
connected at Port B, and apply the proper termination required in each scenario.
The CBTL12131 is powered from a single 3.3 V power supply, consumes very little
current while providing low insertion loss and low return loss high-speed differential switch
channels suitable for use in DisplayPort v1.1a interconnect. All switch and configuration
settings can be performed by board-strapping or driving simple CMOS inputs—no
software or bus configuration is required. CBTL12131 is available in a 6 mm
×
6 mm
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
TFBGA64 package with 0.5 mm ball pitch; owing to its high level of integration and
versatility, it is eminently suitable for use in computers employing bidirectional DisplayPort
video.
2. Features and benefits
2.1 High-speed DisplayPort Main Link multiplexing
Switch path topologies supporting:
‘dual through’ mode (two GPUs to two displays simultaneously)
‘external source’ mode (external source to internal display)
Supports DisplayPort v1.1a at 2.7 Gbit/s
High-bandwidth analog pass-gate technology
Configurable equalization in ‘external source’ mode path
Pre-emphasis level control for equalizer in ‘external source’ mode path
Very low intra-pair differential skew of < 5 ps
Very low inter-pair skew of < 180 ps
2.2 DDC and AUX multiplexing
Switch path topologies supporting:
‘dual through’ mode (two GPUs to two displays)
‘external source’ mode (external source to internal display)
‘AC coupling bypass’ mode on Port A (for external ++DP sink)
Supports DisplayPort v1.1a AUX channel
Supports DDC/I
2
C-bus multiplexing
High-bandwidth analog pass-gate technology
2.3 HPD channel management
Active logic management of HPD signals
Bidirectional HPD I/O for external connector (Port B)
HPD input for integrated DisplayPort display (Port D)
Two HPD outputs to both GPUs, one for internal (Port C) and one for external video
(Port A)
5 V tolerance on all HPD inputs
3.3 V LVTTL logic output levels for all HPD outputs
Internal 200 kΩ pull-down resistor on Port B and Port D HPD input ensures default
LOW when no sink is connected
2.4 Link state detection, configuration and reporting
Detection of DC state of AUX_P and AUX_N lines of external display (Port B)
Filtering of HPD interrupt pulse from external display (Port B)
Reporting of detected/filtered Port B AUX and HPD states via CMOS outputs (to
external system controller)
AUX channel bias control inputs for Port B to allow configuration as source or sink
CBTL12131
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
2 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
Integrated high-ohmic pull-down (4.7 MΩ) and switchable 100 kΩ and 500 kΩ
resistors for Port B AUX bias control
2.5 Equalizer
Programmable equalizer for channel loss compensation from Port B to Port D
(external source mode)
Five levels of input equalization (including flat)
Two levels of output pre-emphasis (including flat)
Two output voltage swing levels
Three quinary input control pins allow equalization, pre-emphasis and output voltage
swing selection by simple board strapping
2.6 General
Power supply 3.3 V
±
10 %
Low active mode supply current of 30 mA typical (Dual-through mode)
Active mode supply current of 120 mA typical (External source mode, EQ = on)
ESD resilience to 4 kV HBM, 1 kV CDM
Available in TFBGA64 6 mm
×
6 mm package
3. Typical system configuration
CBTL12131
GPU1
PRIMARY
VIDEO
(source)
DisplayPort
dual
through mode
PORT C
PORT D
external
source mode
GPU2
SECONDARY
VIDEO
(source)
DisplayPort
dual
through mode
PORT A
PORT B
DP
CONNECTOR
DisplayPort
eDP
CONNECTOR
DisplayPort
INTERNAL
DISPLAY
PANEL
(sink)
DP or ++DP
EXTERNAL
DISPLAY
(sink)
DP
NOTEBOOK
(source)
002aae673
Fig 1.
CBTL12131 in typical system configuration
4. Ordering information
Table 1.
Ordering information
Package
Name
CBTL12131ET
TFBGA64
Description
plastic thin fine-pitch ball grid array package; 64 balls; body 6
×
6
×
0.8 mm
Version
SOT543-1
Type number
CBTL12131
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
3 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
5. Functional diagram
PATH_SEL
Port C
(faces GPU for
internal video)
DDC_AUX_SEL
TST_REXT
PATH_SEL#
ML_C_[3:0]P
ML_C_[3:0]N
PATH_SEL#
AUX_C_P
AUX_C_N
HPD_C
LV5
PL5
EQ5
4
4
4
Port D
(faces eDP
connector)
CBTL12131
4
ML_D_[3:0]P
ML_D_[3:0]N
AUX_D_P
AUX_D_N
HPD_D
PATH_SEL = 0: disabled
EQ PATH_SEL = 1: enabled
PATH_SEL#
and HPD_B_FLT
4
PATH_SEL
RPD_HPD
200 kΩ
ML_A_[3:0]P
ML_A_[3:0]N
ML_B_[3:0]P
ML_B_[3:0]N
DDC_AUX_SEL#
and PATH_SEL#
and HPD_B_FLT
AUX_A_P
100 kΩ
RAUX100_P
500 kΩ
+
RAUX500_P
AUX_B_P
AUX_A_N
+
100 kΩ
RAUX100_N
AUX_B_N
DDC_AUX_SEL
and PATH_SEL#
and HPD_B_FLT
DDC_A_0
DDC_A_1
HPD_A
RAUX4M7N
4.7 MΩ
RAUX4M7P
4.7 MΩ
RPD_HPD
200 kΩ
PATH_SEL = 0:
High-Z
PATH_SEL = 1:
active
HPD_B
AUX_B_P_STATE
AUX_TERM_SRC
AUX_TERM_SNK
VDD
GND
4
3
AUX
TERMINATION
CONFIGURATION
HPD
FILTER
AUX
DETECTION
AUX_B_N_STATE
HPD_B_FLT
002aae674
Port A
(faces GPU for
external video)
Port B
(faces external DP
connector)
(1) Switch is in ON (conducting) position when qualifier = TRUE.
Fig 2.
Functional diagram
CBTL12131
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
4 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL12131ET
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
002aae675
Transparent top view
Fig 3.
Pin configuration for TFBGA64
Port D
(faces eDP connector)
1
A
ML_D_0P
2
ML_D_1P
3
ML_D_2P
4
ML_D_3P
5
HPD_D
6
HPD_B
Port B
(faces external DP connector)
7
ML_B_0P
8
ML_B_1P
9
ML_B_2P
10
ML_B_3P
B
ML_D_0N
ML_D_1N
ML_D_2N
ML_D_3N
VDD
GND
ML_B_0N
ML_B_1N
ML_B_2N
ML_B_3N
C
AUX_D_P
AUX_B_
P_STATE
PATH_
SEL
TST_
REXT
AUX_
TERM_
SRC
AUX_C_P
AUX_D_N
AUX_B_
N_STATE
VDD
Transparent top view
AUX_B_N
AUX_B_P
DDC_
AUX_SEL
EQ5
HPD_B_
FLT
DDC_A_0
D
PL5
E
VDD
F
GND
AUX_
TERM_
SNK
AUX_C_N
LV5
G
DDC_A_1
H
AUX_A_N
AUX_A_P
J
ML_C_0N
ML_C_1N
ML_C_2N
ML_C_3N
VDD
GND
ML_A_0N
ML_A_1N
ML_A_2N
ML_A_3N
K
ML_C_0P
ML_C_1P
ML_C_2P
ML_C_3P
HPD_C
HPD_A
ML_A_0P
ML_A_1P
ML_A_2P
ML_A_3P
002aae676
Port C
(faces GPU for internal video)
Port A
(faces GPU for external video)
Fig 4.
CBTL12131
Ball mapping for TFBGA64
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
5 of 28
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