CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
Rev. 3 — 24 September 2013
Product data sheet
1. General description
The CBT3253A is a dual 1-of-4 high-speed TTL-compatible FET
multiplexer/demultiplexer. The low ON-resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or generating additional ground
bounce noise.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
The CBT3253A is characterized for operation from
40 C
to +85
C.
2. Features and benefits
5
switch connection between two ports
TTL-compatible input levels
Minimal propagation delay through the switch
Latch-up protection exceeds 100 mA per JEDEC standard JESD78 class II level A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
3. Ordering information
Table 1.
Ordering information
Temperature range
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Package
Name
CBT3253AD
CBT3253ADB
CBT3253ADS
CBT3253APW
SO16
SSOP16
SSOP16
[1]
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic shrink small outline package; 16 leads;
body width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT519-1
SOT403-1
Type number
[1]
Also known as QSOP16.
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
4. Functional diagram
1A
7
6
5
4
3
1B1
1B2
1B3
1B4
2B1
2B2
2B3
2B4
2A
9
10
11
12
13
S0
14
S1
2
1OE
1
2OE
15
002aab828
Fig 1.
Logic diagram
CBT3253A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 September 2013
2 of 15
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
CBT3253A
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
2
3
4
5
6
7
8
002aab824
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
9
2A
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
2
3
4
5
6
7
8
002aab827
CBT3253A
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
9
2A
Fig 2.
Pin configuration SOT109-1 (SO16) and
SOT519-1 (SSOP16)
Fig 3.
Pin configuration SOT338-1 (SSOP16) and
SOT403-1 (TSSOP16)
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
S1, S0
1B4, 1B3, 1B2, 1B1
1A
GND
2A
2B1, 2B2, 2B3, 2B4
V
CC
Pin description
Pin
1, 15
2, 14
3, 4, 5, 6
7
8
9
10, 11, 12, 13
16
Description
output enable (active LOW)
select control input
1B outputs/inputs
1A input/output
ground (0 V)
2A input/output
2B outputs/inputs
positive supply voltage
CBT3253A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 September 2013
3 of 15
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
6. Functional description
Table 3.
Function selection
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Inputs
1OE
X
H
L
L
L
L
2OE
H
X
L
L
L
L
S1
X
X
L
L
H
H
S0
X
X
L
H
L
H
disconnect 1A and 2A
disconnect 1A and 2A
1A to 1B1 and 2A to 2B1
1A to 1B2 and 2A to 2B2
1A to 1B3 and 2A to 2B3
1A to 1B4 and 2A to 2B4
Switch
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
CC
V
I
I
SW
I
IK
T
stg
P
tot
supply voltage
input voltage
switch current
input clamping current
storage temperature
total power dissipation
T
amb
=
40 C
to +85
C
SO16 package
SSOP16 package
TSSOP16 package
[1]
[2]
[3]
[2]
[3]
[3]
[1]
Conditions
Min
0.5
0.5
-
50
65
-
-
-
Max
+7.0
+7.0
128
+150
500
500
500
Unit
V
V
mA
mA
C
mW
mW
mW
continuous current through each switch
V
I
< 0 V
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP16 and TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 70
C.
8. Recommended operating conditions
Table 5.
Operating conditions
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
Symbol
V
CC
V
IH
V
IL
T
amb
Parameter
supply voltage
HIGH-level input voltage
LOW-level input voltage
ambient temperature
operating in free-air
Conditions
Min
4.5
2.0
-
40
Max
5.5
-
0.8
+85
Unit
V
V
V
C
CBT3253A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 September 2013
4 of 15
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
T
amb
=
40
C to +85
C.
Symbol
V
IK
V
pass
I
I
I
CC
I
CC
C
I
C
io(off)
C
io(on)
R
ON
Parameter
input clamping voltage
pass voltage
input leakage current
supply current
additional supply current
input capacitance
off-state input/output capacitance
on-state input/output capacitance
ON resistance
Conditions
V
CC
= 4.5 V; I
I
=
18
mA
V
I
= V
CC
= 5.0 V; I
O
=
100 A
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
O
= 0 mA;
V
I
= V
CC
or GND
per input; V
CC
= 5.5 V; one input at
3.4 V, other inputs at V
CC
or GND
control pins; V
I
= 3 V or 0 V
A port; V
O
= 3 V or 0 V; nOE = V
CC
B port; V
O
= 3 V or 0 V; nOE = V
CC
A port and B port
V
CC
= 4.5 V
V
I
= 0 V; I
I
= 64 mA
V
I
= 0 V; I
I
= 30 mA
V
I
= 2.4 V; I
I
= 15 mA
[1]
[2]
[3]
All typical values are measured at V
CC
= 5 V; T
amb
= 25
C.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. The lowest voltage of the
two (A or B) terminals determines the ON resistance.
[3]
[2]
Min
-
3.6
-
-
-
-
-
-
-
-
-
-
Typ
[1]
-
3.9
-
-
-
4.5
11.4
3.8
18.6
5
5
10
Max
1.2
4.2
1
3
2.5
-
-
-
-
7
7
15
Unit
V
V
A
A
mA
pF
pF
pF
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
T
amb
=
40
C to +85
C; V
CC
= 4.5 V to 5.5 V; for test circuit, see
Figure 6.
Symbol
t
pd
t
en
t
dis
Parameter
propagation delay
enable time
disable time
Conditions
nA to nBn or nBn to nA; see
Figure 4
Sn to nA; see
Figure 4
nOE to nA or nBn; see
Figure 5
Sn to nBn; see
Figure 5
nOE to nA or nBn; see
Figure 5
Sn to nBn; see
Figure 5
[1]
[2]
[1][2]
[1][2]
[2]
[2]
[2]
[2]
Min
-
1.2
1.3
1.4
1.1
1.0
Max
0.25
6.2
6.3
6.4
7.2
7
Unit
ns
ns
ns
ns
ns
ns
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON
resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).
t
PLH
and t
PHL
are the same as t
pd
.
t
PZL
and t
PZH
are the same as t
en
.
t
PLZ
and t
PHZ
are the same as t
dis
.
CBT3253A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 September 2013
5 of 15
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