CAT130xx
Voltage Supervisor with
Microwire Serial CMOS
EEPROM
Description
The CAT130xx (see table below) are memory and supervisory
solutions for microcontroller based systems. A CMOS serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together. Memory interface is via Microwire
serial protocol.
The CAT130xx provides a precision V
CC
sense circuit with two reset
output options: CMOS active low output or CMOS active high. The
RESET output is active whenever V
CC
is below the reset threshold or
falls below the reset threshold voltage.
The power supply monitor and reset circuit protect system
controllers during power up/down and against brownout conditions.
Seven reset threshold voltages support 5 V, 3.3 V, 3 V and 2.5 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
240 ms after the supply voltage exceeds the reset threshold level.
Features
♦
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SOIC−8
CASE 751BD
PIN CONFIGURATION
SOIC (W)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
V
CC
RST/RST
ORG
GND
•
Precision Power Supply Voltage Monitor
•
•
•
•
•
•
•
•
•
PIN FUNCTION
Pin Name
CS
SK
DI
DO
GND
ORG
RST/RST
V
CC
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Ground
Memory Organization
Reset Output
Power Supply
5 V, 3.3 V, 3 V and 2.5 V Systems
♦
7 Threshold Voltage Options
Active High or Low Reset
♦
Valid Reset Guaranteed at V
CC
= 1 V
High Speed Operation
Selectable x8 or x16 Memory Organization
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
RoHS−Compliant 8−Pin SOIC Package
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
THRESHOLD SUFFIX SELECTOR
Nominal Threshold Voltage
4.63 V
4.38 V
4.00 V
3.08 V
2.93 V
2.63 V
2.32 V
Threshold Suffix
Designation
L
M
J
T
S
R
Z
NOTE:
When the ORG pin is connected to V
CC
, the x16
organization is selected. When it is connected to
ground, the x8 pin is selected. If the ORG pin is left
unconnected, then an internal pullup device will
select the x16 organization.
MEMORY SIZE SELECTOR
Product
13001
13004
13008
13016
Memory Density
1−Kbit
4−Kbit
8−Kbit
16−Kbit
ORDERING INFORMATION
For Ordering Information details, see page 10.
1
Publication Order Number:
CAT13001/D
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 3
CAT130xx
BLOCK DIAGRAM
V
CC
DO
ORG
CS
SK
DI
EEPROM
VOLTAGE
DETECTOR
RST or RST
V
SS
SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
NEND (Note 3)
TDR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5 V to +5.5 V, unless otherwise specified.
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL
V
OH
Parameter
Supply Current
Standby Current
Test Conditions
Read or Write at 1 MHz
V
CC
< 5.5 V; All I/O Pins at V
SS
or V
CC
V
CC
< 3.6 V; All I/O Pins at V
SS
or V
CC
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
CC
≥
2.5 V, I
OL
= 2.1 mA
V
CC
≥
4.5 V, I
OL
=
−0.4
mA
2.4
Pin at GND or V
CC
−0.5
2.0
12
10
Min
Typ
Max
3
25
20
2
0.8
V
CC
+ 0.5
0.4
mA
V
V
V
V
Units
mA
mA
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CAT130xx
Table 4. A.C. CHARACTERISTICS (MEMORY)
(Note 1)
V
CC
= +2.5 V to 5.5 V, T
A
=
−40°C
to 85°C, unless otherwise specified.
Symbol
f
SK
t
CSS
t
CSH
t
CSMIN
t
SKHI
t
SKLOW
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 1)
t
SV
t
EW
t
PU
(Notes 2 & 3)
1.
2.
3.
Clock Frequency
CS Setup Time
CS Hold Time
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Output Delay to Status Valid
Program/Erase Pulse Width
Power−up to Ready Mode
Parameter
Min
DC
50
0
0.25
0.25
0.25
100
100
0.25
0.25
100
0.25
5
1
Max
2000
Units
kHz
ns
ns
ms
ms
ms
ns
ns
ms
ms
ns
ms
ms
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 5. A.C. TEST CONDITIONS
Parameter
Input Rise and Fall Times
Input Levels
Input Levels
Timing Reference Levels
Timing Reference Levels
Output Load
Test Conditions
≤50
ns
0.4 V to 2.4 V (4.5 V < V
CC
< 5.5 V)
0.2 V
CC
to 0.7 V
CC
(2.5 V < V
CC
< 4.5 V)
0.8 V, 2.0 V (4.5 V < V
CC
< 5.5 V)
0.5 V
CC
(2.5 V < V
CC
< 4.5 V)
Current Source: I
OL max
/ I
OH max
; C
L
= 100 pF
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CAT130xx
Table 6. ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
V
CC
= Full range, T
A
=
−40°C
to +85°C unless otherwise noted. Typical values at T
A
= +25°C and V
CC
= 5 V for L/M/J versions,
V
CC
= 3.3 V for T/S versions, V
CC
= 3 V for R version and V
CC
= 2.5 V for Z version.
Symbol
V
TH
Parameter
Reset Threshold
Voltage
Threshold
L
T
A
= +25°C
T
A
=
−40°C
to +85°C
M
T
A
= +25°C
T
A
=
−40°C
to +85°C
J
T
A
= +25°C
T
A
=
−40°C
to +85°C
T
T
A
= +25°C
T
A
=
−40°C
to +85°C
S
T
A
= +25°C
T
A
=
−40°C
to +85°C
R
T
A
= +25°C
T
A
=
−40°C
to +85°C
Z
T
A
= +25°C
T
A
=
−40°C
to +85°C
Symbol
Parameter
Reset Threshold Tempco
t
RPD
t
PURST
V
OL
V
CC
to Reset Delay (Note 2)
Reset Active Timeout Period
RESET Output Voltage Low
(Push−pull, Active LOW,
CAT130xx9)
V
CC
= V
TH
to (V
TH
−100
mV)
T
A
=
−40°C
to +85°C
V
CC
= V
TH
min, I
SINK
= 1.2 mA
R/S/T/Z
V
CC
= V
TH
min, I
SINK
= 3.2 mA
J/L/M
V
CC
> 1.0 V, I
SINK
= 50
mA
V
OH
RESET Output Voltage High
(Push−pull, Active LOW,
CAT130xx9)
V
CC
= V
TH
max, I
SOURCE
=
−500
mA
R/S/T/Z
V
CC
= V
TH
max, I
SOURCE
=
−800
mA
J/L/M
V
CC
> V
TH
max, I
SINK
= 1.2 mA
R/S/T/Z
V
CC
> V
TH
max, I
SINK
= 3.2 mA
J/L/M
1.8 V < V
CC
≤
V
TH
min,
I
SOURCE
=
−150
mA
0.8 V
CC
0.8 V
CC
V
CC
−
1.5
0.3
0.4
V
V
140
Conditions
Conditions
Min
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
Min
Typ
(Note 1)
30
20
240
460
0.3
0.4
0.3
V
2.32
2.63
2.93
3.08
4.00
4.38
Typ
4.63
Max
4.70
4.75
4.45
4.50
4.06
4.10
3.11
3.15
2.96
3.00
2.66
2.70
2.35
2.38
Max
Units
ppm/°C
ms
ms
V
Units
V
V
OL
RESET Output Voltage Low
(Push−pull, Active HIGH,
CAT130xx1)
V
OH
RESET Output Voltage High
(Push−pull, Active HIGH,
CAT130xx1)
1. Production testing done at T
A
= +25°C; limits over temperature guaranteed by design only.
2. RESET output for the CAT130xx9; RESET output for the CAT130xx1.
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CAT130xx
PIN DESCRIPTION
RESET/RESET:
The reset output is available in two
versions: CMOS Active Low (CAT130xx9) and CMOS
Active High (CAT130xx1). Both versions are push−pull
outputs for high efficiency.
DI:
The serial data input pin accepts op−codes, addresses
and data. The input data is latched on the rising edge of the
SK clock input.
SK:
The serial clock input pin accepts the clock provided by
the host and used for synchronizing communication
between host and CAT130xx device.
CS:
The chip select input pin is used to enable/disable the
CAT130xx. When CS is high, the device is selected and
accepts op−codes, addresses and data. Upon receiving a
Write or Erase instruction, the falling edge of CS will start
the internal write cycle to the selected memory location.
ORG:
The memory organization input selects the memory
configuration as either register of 16 bits (ORG tied to V
CC
or floating) or 8 bits (ORG connected to GND).
DEVICE OPERATION
The CAT130xx products combine the accurate voltage
monitoring capabilities of a standalone voltage supervisor
with the high quality and reliability of standard EEPROMs
from ON Semiconductor.
Reset Controller Description
initial voltage of 0.5 V above the threshold and drops below
it by the amplitude of the overdrive voltage (V
TH
−
V
CC
).
TRANSIENT DURATION [μs]
T
AMB
= 25ºC
The reset signal is asserted LOW for the CAT130xx9 and
HIGH for the CAT130xx1 when the power supply voltage
falls below the threshold trip voltage and remains asserted
for at least 140 ms (t
PURST
) after the power supply voltage
has risen above the threshold. Reset output timing is shown
in Figure 2.
The CAT130xx devices protect
mPs
against brownout
failure. Short duration V
CC
transients of 4
msec
or less and
100 mV amplitude typically do not generate a Reset pulse.
Figure 1 shows the maximum pulse duration of
negative−going V
CC
transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing V
TH
−
V
CC
), the maximum
pulse duration decreases. In this test, the V
CC
starts from an
CAT130xxZ
CAT130xxM
RESET OVERDRIVE V
TH
- V
CC
[mV]
Figure 1. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
V
TH
V
CC
V
RVALID
t
PURST
t
RPD
t
PURST
t
RPD
RESET
CAT130xx9
RESET
CAT130xx1
Figure 2. RESET Output Timing
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