MK1726A
Low EMI Clock Generator
Description
The MK1726-01A/-02A/-04A devices generate a low
EMI output clock from a clock or crystal input. The part
is designed to dither the LCD interface clock for PDAs,
printers, scanners, modems, copiers, etc. Using ICS’
proprietary mix of analog and digital Phase Locked
Loop (PLL) technology, the device spreads the
frequency spectrum of the output and reduces the
frequency amplitude peaks by several dB. The
MK1726-01A/-02A/-04A devices offer both centered
and down spread from a high-speed clock input.
ICS offers many other clocks for computers and
computer peripherals. Consult ICS when you need to
remove crystals and oscillators from your board.
Features
•
•
•
•
•
•
•
•
Packaged in 8-pin SOIC/TSSOP
Provides a spread spectrum output clock
Supports flat panel controllers
Accepts a clock or crystal input (provides same
frequency dithered output)
Input frequency range of 4 to 32 MHz.
Output frequency range of 4 to 128 MHz
1X, 2X, 4X frequency multiplication
1X: MK1726-01A; 2X: MK1726-02A; 4X:
MK1726-04A
•
Center and down spread
•
Peak reduction by 8 dB to 16 dB typical on 3rd
through 19th odd harmonics
•
•
•
•
Low EMI feature can be disabled
Includes power down
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
Spread Direction
FRSEL
2
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
X1= 01A
X2= 02A
X4= 04A
SSCLK
X1/CLK
Clock Buffer/
Crystal
Ocsillator
X2
The crystal requires external capacitors
for accurate tuning of the clock
GND
MDS 1726A B
Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 101703
www.icst.com
MK1726A
Low EMI Clock Generator
Pin Assignment
Spread Direction and Spread
Percentage
8
7
6
5
X2
VDD
FRSEL
SSCLK
X1/ICLK
GND
S1
S0
1
2
3
4
S1
Pin 3
0
0
0
M
M
M
1
1
1
S0
Pin 4
0
M
1
0
M
1
0
M
1
Spread
Direction
Center
Center
Center
Center
No Spread
Down
Down
Down
Down
Spread
Percentage
±1.4
±1.1
±0.6
±0.5
-
-1.6
-2.0
-0.7
-3.0
8-pin (150 mil) SOIC/TSSOP
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
Frequency Selection
Product
MK1726-01A
MK1726-01A
MK1726-01A
MK1726-02A
MK1726-02A
MK1726-02A
MK1726-04A
MK1726-04A
MK1726-04A
FRSEL
(pin 6)
0
1
M
0
1
M
0
1
M
Input
Freq. Range
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
Multiplier
X1
X1
X1
X2
X2
X2
X4
X4
X4
Output
Freq. Range
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
32.0 to 64.0MHz
16.0 to 32.0MHz
32.0 to 64.0MHz
64.0 to 128MHz
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
MDS 1726A B
Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 101703
www.icst.com
MK1726A
Low EMI Clock Generator
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
X1/ICLK
GND
S1
S0
SSCLK
FRSEL
VDD
X2
Input
Power
Input
Input
Output
Input
Power
XO
Connect to 4-32 MHz crystal or clock.
Connect to ground.
Function select 1 input. Selects spread amount and direction per table above.
(default-internal mid-level).
Function select 0 input. Selects spread amount and direction per table above.
(default-internal mid-level).
Clock output with Spread spectrum
Function select for input frequency range. Default to mid level “M”.
Connect to +3.3 V.
Crystal connection to 4-32 MHz crystal. Leave unconnected for clock
External Components
The MK1726-01A/-02A/-04A devices require a
minimum number of external components for proper
operation.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, observe the following guidelines:
1) Mount the 0.01µF decoupling capacitor on the
component side of the board as close to the VDD pin
as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to
the VDD pin and the PCB trace to the ground via
should be kept as short as possible.
2) To minimize EMI, place the 33Ω series-termination
resistor (if needed) close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, thus minimizing vias through
other signal layers. Other signal traces should be
routed away from the MK1726A devices. This includes
signal traces located underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 7 and 2. Connect the
capacitor as close to these pins as possible. For
optimum device performance, mount the decoupling
capacitor on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
Use series termination when the PCB trace between
the clock output and the load is over 1 inch. To series
terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the
clock line. Place the resistor as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20Ω.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant crystal. To
optimize the initial accuracy, connect crystal capacitors
from pins X1 to ground and X2 to ground. The value of
these capacitors is given by the following equation:
Crystal caps (pF) = (C
L
- 6) x 2
Tri-level Select Pin Operation
The S1 and S0 select pins are tri-level, meaning that
they have three separate states to make the selections
shown in the table on page 2. To select the M (mid)
level, the connection to these pins must be eliminated
by either floating them originally, or tri-stating the GPIO
pins which drive the select pins.
MDS 1726A B
Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 101703
www.icst.com
MK1726A
Low EMI Clock Generator
In the equation, C
L
is the crystal load capacitance. For
example, a crystal with a 16 pF load capacitance uses
two 20 pF [(16-6) x 2] capacitors.
Modulation R
ate
Spread Spectrum Profile
The MK1726-01A/-02A/-04A device’s low EMI clock
generator uses an optimized frequency slew rate
algorithm to facilitate down stream tracking of zero
delay buffers and other PLL devices.
Frequency
Time
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1726A devices. These
ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional
operation of the device, at these or any other conditions, above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +85°C
-65 to +150°C
175°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
3.63
Units
°C
V
MDS 1726A B
Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 101703
www.icst.com
MK1726A
Low EMI Clock Generator
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±10%,
Ambient Temperature 0 to +85°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
IDD
Conditions
No load, at 3.3 V, Fin=12 MHz
No load, at 3.3 V, Fin=24 MHz
No load, at 3.3 V, Fin=32 MHz
Min.
3.0
Typ.
3.3
23
Max.
3.63
25
30
35
Units
V
mA
mA
mA
V
V
V
V
V
Input High Voltage
Input middle Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
V
IH
V
IHM
V
IL
V
OH
V
OH
V
OL
C
IN1
C
IN2
CMOS, I
OH
= -4 mA
I
OH
= -6 mA
I
OL
= -4 mA
I
OL
= -10 mA
S0, S1, FRSEL pins
X1, X2 pins
0.85VDD
0.4VDD
0.0
2.4
2.0
VDD
0.5VDD
0.0
VDD
0.6
0.15
0.4
1.2
4
6
6
9
V
V
pF
pF
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±10%,
Ambient Temperature 0 to +85° C, C
L
= 15 pF
Parameter
Input Clock Frequency
Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-cycle Jitter (-01A)
Cycle-to-cycle Jitter (-01A)
Cycle-to-cycle Jitter (-02A)
Cycle-to-cycle Jitter (-02A)
Cycle-to-cycle Jitter (-04A)
Cycle-to-cycle Jitter (-04A)
Output Rise Time (-01A, -02A)
Output Fall Time (-01A, -02A)
FSEL = M (-04A only)
FSEL = 1, 0 (-04A only)
EMI Peak Frequency Reduction
Symbol
Conditions
Min.
4
4
Typ.
Max. Units
32
128
60
MHz
MHz
%
%
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
dB
Time above VDD/2
Time above 1.5 V
Fin=4MHz, Fout=4 MHz
Fin=8MHz, Fout=8 MHz
Fin=8MHz, Fout=16 MHz
Fin=16MHz, Fout=32 MHz
Fin=16MHz,Fout=64 MHz
Fin=32MHz, Fout=128 MHz
t
R
t
F
t
R
t
R
t
F
t
F
0.4 to 2.4 V
2.4 to 0.4 V
40
45
50
350
260
260
260
360
360
2.0
2.0
1.2
1.2
2.2
2.2
3.2
3.2
2.2
2.2
4.3
4.3
8 to 16
55
800
550
550
550
800
800
5.0
4.4
3.6
3.6
6.9
6.9
MDS 1726A B
Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 101703
www.icst.com
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