that share 64 product terms. The PA7536’s logic and I/O
cells (LCCs, IOCs) are extremely flexible offering up to
three output functions per cell (a total of 36 for all 12 logic
cells). Cells are configurable as D, T, and JK registers with
independent or global clocks, resets, presets, clock polarity,
and other special features, making the PA7536 suitable for
a variety of combinatorial, synchronous and asynchronous
logic applications. The PA7536 offers pin compatibility and
super-set functionality to popular 28-pin PLDs, such as the
26V12. Thus, designs that exceed the architectures of
such devices can be expanded upon. The PA7536
supports speeds as fast as 9ns/15ns (tpdi/tpdx) and
83.3MHz (f
MAX
) at moderate power consumption 105mA
(75mA typical). Packaging includes 28-pin DIP, SOIC, and
PLCC (see Figure 1). Development and programming
support for the PA7536 is provided by Anachip and popular
third-party development tool manufacturers.
Figure 1. Pin Configuration
I/CLK1
I
I
I
I
I
VCC
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/CLK1
I/CLK2
I/O
I/O
I
I
I
I/CLK1
I
I
I
I
I
VCC
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
Figure 2. Block Diagram
2 Input/
Global Clock Pins
Global
Cells
76 (38X2)
Array Inputs
true and
complement
12
Buried
logic
Logic functions
to I/O cells
I/O
Cells
(IOC)
12 I/O Pins
12 Input Pins
Input
Cells
(IN C)
2
12
SOIC
I/O
I/O
12
I/CLK1
I
I
I
I
Input Cells
I/O Cells
Global Cells
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
Logic Control Cells
I/O
I/O
I/O
Logic
Array
DIP
4
I
I
VCC
I
I
I
I
5
6
7
8
9
10
11
12 13 14 15 16 17 18
I/O
I/O
I/O
I/O
3
2
1 28 27 26
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
GND
I/O
I/O
A
B
C
D
Logic
C ontrol
Cells
(LCC)
12
12
I
VCC
I
I
I
I
I
I
I
08-16-001A
2 sum terms
3 product terms
for Global C ells
48 sum terms
(four per LCC)
12 Logic Control Cells
up to 3 output functions per cell
(36 total output functions possible)
PLCC
PA7536
08-16-002A
I
I
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
I
Rev. 1.0 Dec 16, 2004
1/10
To find out if the package you need is
available, contact Customer Service
Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. Depending on the PEEL™ Array selected, a
range of 38 to 62 inputs is available into the array from the
I/O cells, inputs cells and input/global-clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
number of product-terms among PEEL™ Arrays ranges
from 67 to 125. All product terms (with the exception of
certain ones fed to the global cells) can be programmably
connected to any of the sum-terms of the logic control cells
(four sum-terms per logic control cell). Product-terms and
sum-terms are also routed to the global cells for control
purposes. Figure 3 shows a detailed view of the logic
array structure.
ensures that product-terms are used where they are
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can
be used for clocks, resets, presets and output enables
instead of just simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product
terms to implement 16 exclusive-OR functions. The
PEEL™ logic array easily handles this in a single level
delay. Other PLDs/CPLDs either run out of product-terms
or require expanders or additional logic levels that often
slow performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control
the logic functions created in the logic array. Each LCC has
four primary inputs and three outputs. The inputs to each
LCC are complete sum-of-product logic functions from the
array, which can be used to implement combinatorial and
sequential logic functions, and to control LCC registers and
I/O cell output enables.
From Global Cell
System Clock
Preset
RegType Reset
From
IO Cells
(IOC,INC,
I/CLK)
38 Array Inputs
On/Off
From
Logic
Control
Cells
(LCC)
MUX
P
D ,T,J
Q
To
Array
MUX
K
REG
R
To
Global
Cells
67 Product Terms
From
Array
A
B
C
D
MUX
To
I/O
Cell
To
Logic Control
Cells
(LCC)
08-16-004A
08-16-003A
PA7536 Logic Array
50 Sum Terms
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with
synchronous or asynchronous D, T, or JK registers
(clocked-SR registers, which are a subset of JK, are also
possible). See Figure 5. EEPROM memory cells are used
for programming the desired configuration. Four sum-of-
product logic functions (SUM terms A, B, C and D) are fed
into each LCC from the logic array. Each SUM term can be
selectively used for multiple functions as listed below.
Rev. 1.0 Dec 16, 2004
2/10
Figure 3 PA7536 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
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Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
D
P
D Register
Q = D after clocked
Q
Best for storage, sim ple counters,
shifters and state m achines with
few hold (loop) conditions.
can be registered, one output can be combinatorial and the
third, an output enable or an additional buried logic function.
The multi-function PEEL™ Array logic cells are equivalent
to two or three macrocells of other PLDs, which have only
one output per cell. They also allow registers to be truly
buried from I/O pins without limiting them to input-only (see
Figure 8 and Figure 9).
From Global Cell
Input Cell Clock
R
T
P
Q
T Register
Q toggles when T = 1
Q holds when T = 0
Best for wide binary counters (saves
product terms) and state m achines
with m any hold (loop) conditions.
R
REG/
Latch
Q
J
K
P
Q
JK Register
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q =1
when J/K = 1/0
Q =0
when J/K = 0/1
Com bines features of both D and T
registers.
08-16-005A
Input
M UX
Input
To
Array
Input Cell (INC)
R
From Global Cell
Input Cell Clock
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 11).
Q
REG/
Latch
To
Array
Input
M UX
M UX
From
Logic
Control
Cell
A,B,C
or
Q
M UX
I/O Pin
M UX
D
1 0
I/O Cell (IOC)
08-16-006A
Figure 6. I/O Cell Block Diagram
D
Q
IOC/INC Register
Q = D after rising edge of clock
holds until next rising edge
L
Q
IOC/INC Latch
Q = L when clock is high
holds value when clock is low
08-16-007A
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C combinatorial paths. Thus, one LCC output
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Figure 7. IOC Register Configurations
Rev. 1.0 Dec 16, 2004
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available, contact Customer Service
Input Cells (INC)
Input cells (INC) are included on dedicated input pins. The
block diagram of the INC is shown in Figure 6. Each INC
consists of a multiplexer and a register/transparent latch,
which can be clocked from various sources selected by the
global cell. The register is rising edge clocked. The latch is
transparent when the clock is high and latched on the
clock’s failing edge. The register/latch
can also be
bypassed for a non registered input.
Global Cells
The global cells, shown in Figure 10, are used to direct
global clock signals and/or control terms to the LCCs, IOCs
and INCs. The global cells allow a clock to be selected
from the CLK1 pin, CLK2 pin, or a product term from the
logic array (PCLK). They also provide polarity control for
IOC clocks enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has
its own polarity control. The global cell includes sum-of-
products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to
save product terms for loadable counters and state
machines (see Figure 11). The PA7536 provides two
global cells that divide the LCC and IOCs into two groups,
A and B. Half of the LCCs and IOCs use global cell A, half
use global cell B. This means, for instance, two high-speed
global clocks can be used among the LCCs.
CLK1
CLK2
M UX
PCLK
INC Clocks
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-
state buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a non-
registered input. A feature of the 7536 IOC is the use of
SUM-D as a feed-back to the array when the I/O pin is a
dedicated output. This allows for additional buried registers
and logic paths. (See Figure 8 & Figure 9).
Global Cell: INC
Group A & B
CLK1
Q D
M UX
LCC Clocks
Input with optional
register/latch
CLK2
I/O
M UX
PCLK
Reg-Type
IOC Clocks
LCC Reg-Type
LCC Presets
LCC Resets
I/O with
independent
output enable
A
B
C
D
D Q
Preset
Reset
1
2
OE
08-16-008A
Global Cell: LCC & IOC
08-16-010A
Figure 10. Global Cells
Reg-Type from Global Cell
Figure 8. LCC & IOC With Two Outputs
Register Type Change Feature
Q D
D
P
Q
Buried register or
logic paths
Output
R
Global Cell can dynam ically change user-
selected LCC registers from D to T or from D
to JK. This saves product terms for loadable
counters or state m achines. Use as D register
to load, use as T or JK to count. Tim ing allows
dynam ic operation.
A
B
C
D
D Q
1
2
3
T
08-16-009A
P
Example:
Product terms for 10 bit loadable binary counter
Q
D uses 57 product term s (47 count, 10 load)
T uses 30 product term s (10 count, 20 load)
D/T uses 20 product term s (10 count, 10 load)
08-16-011A
R
Figure 9. LCC & IOC With Three Outputs
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4/10
Figure 11. Register Type Change Feature
Rev. 1.0 Dec 16, 2004
To find out if the package you need is
available, contact Customer Service
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful PLACE Development Software
(free to qualified PLD designers). The PLACE software
includes an architectural editor, logic compiler, waveform
simulator, documentation utility and a programmer
interface. The PLACE editor graphically illustrates and
controls the PEEL™ Array’s architecture, making the
overall design easy to understand, while allowing the
effectiveness of boolean logic equations, state machine
design and truth table entry. The PLACE compiler performs
logic transformation and reduction, making it possible to
specify equations in almost any fashion and fit the most
logic possible in every design. PLACE also provides a
multi-level logic simulator allowing external and internal
signals to be simulated and analyzed via a waveform
display.(See Figure 12, Figure 13 and Figure 14)
Programming of PEEL™ Arrays is supported by popular
third party programmers.
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 13 - PLACE LCC and IOC screen
Figure 12 - PLACE Architectural Editor for
PA7536
PEEL™ Array development is also supported by popular
development tools, such as ABEL and CUPL, via ICT’s
PEEL™ Array fitters. A special smart translator utility adds
the capability to directly convert JEDEC files for other
devices into equivalent JEDEC files for pin-compatible
PEEL™ Arrays.
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE-
reprogrammability is also useful for production, allowing
unexpected changes to be made quickly and without waste.
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