MX29LV017B
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 2,097,152 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte Programming (9us typical)
- Sector Erase (Sector structure 64K-Byte x32)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
16M-BIT [2Mx8] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
- Data polling & Toggle bit for detection of program and
erase operation completion.
Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors.
CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Low VCC write inhibit is equal to or less than 1.4V
Package type:
- 40-pin TSOP
- 48-ball CSP
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
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GENERAL DESCRIPTION
The MX29LV017B is a 16-mega bit Flash memory orga-
nized as 2M bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29LV017B is
packaged in 40-pin TSOP and 48-ball CSP. It is de-
signed to be reprogrammed and erased in system or in
standard EPROM programmers.
The standard MX29LV017B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV017B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV017B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV017B uses a 2.7V~3.6V VCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
P/N:PM1086
REV. 1.0, MAR. 18, 2004
1
MX29LV017B
PIN CONFIGURATIONS
40 TSOP (Standard Type) (10mm x 20mm)
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
A20
A19
A10
Q7
Q6
Q5
Q4
VCC
VCC
NC
Q3
Q2
Q1
Q0
OE
GND
CE
A0
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A20
Q0~Q7
CE
WE
RESET
OE
RY/BY
VCC
GND
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Hardware Reset Pin/Sector Protect Unlock
Output Enable Input
Ready/Busy Output
Power Supply Pin (2.7V~3.6V)
Ground Pin
MX29LV017B
48-Ball CSP (Ball Pitch=0.8mm) Top View, Balls Facing Down
A
B
C
D
E
F
G
H
6
A14
A13
A15
A16
A17
NC
A20
GND
5
A9
A8
A11
A12
A19
A10
Q6
Q7
4
WE
RESET
NC
NC
Q5
NC
VCC
Q4
6.0 mm
3
RY/BY
NC
NC
NC
Q2
Q3
VCC
NC
2
A7
A18
A6
A5
Q0
NC
NC
Q1
1
A3
A4
A2
A1
A0
CE
OE
GND
8.0 mm
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REV. 1.0, MAR. 18, 2004
2
MX29LV017B
BLOCK STRUCTURE
Table 1: MX29LV017B SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address Range (in hexadecimal)
000000-00FFFF
010000-01FFFF
020000-02FFFF
030000-03FFFF
040000-04FFFF
050000-05FFFF
060000-06FFFF
070000-07FFFF
080000-08FFFF
090000-09FFFF
0A0000-0AFFFF
0B0000-0BFFFF
0C0000-0CFFFF
0D0000-0DFFFF
0E0000-0EFFFF
0F0000-0FFFFF
100000-10FFFF
110000-11FFFF
120000-12FFFF
130000-13FFFF
140000-14FFFF
150000-15FFFF
160000-16FFFF
170000-17FFFF
180000-18FFFF
190000-19FFFF
1A0000-1AFFFF
1B0000-1BFFFF
1C0000-1CFFFF
1D0000-1DFFFF
1E0000-1EFFFF
1F0000-1FFFFF
P/N:PM1086
REV. 1.0, MAR. 18, 2004
3
MX29LV017B
BLOCK DIAGRAM
CE
OE
WE
RESET
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
ARRAY
SOURCE
HV
X-DECODER
ADDRESS
LATCH
A0-A20
AND
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
P/N:PM1086
REV. 1.0, MAR. 18, 2004
4
MX29LV017B
AUTOMATIC PROGRAMMING
The MX29LV017B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29LV017B is less than 18 sec-
onds.
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV017B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, Table 7, for
more information on these status bits.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SELECT
AUTOMATIC SECTOR ERASE
The MX29LV017B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0. This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9. Other address pin A6, A1 and A0 as referring to
Table 2. In addition, to access the automatic select codes
in-system, the host can issue the automatic select com-
mand through the command register without requiring
VID, as shown in Table 4.
To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
REV. 1.0, MAR. 18, 2004
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
P/N:PM1086
5
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