BLS7G2325L-105
Power LDMOS transistor
Rev. 2 — 19 July 2011
Product data sheet
1. Product profile
1.1 General description
105 W LDMOS power transistor for S-band radar applications at frequencies from
2300 MHz to 2500 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in a common source class-AB production test circuit.
Mode of operation
Pulse CW
f
(MHz)
2300 to 2500
I
Dq
(mA)
900
V
DS
(V)
30
P
L(AV)
(W)
110
G
p
(dB)
16.5
D
(%)
55
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low R
th
providing excellent thermal stability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for S-band radar applications in the 2300 MHz to 2500 MHz
frequency range
NXP Semiconductors
BLS7G2325L-105
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
Pinning
Description
drain
gate
source
[1]
Simplified outline
1
3
2
Graphic symbol
1
2
3
sym112
[1]
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name Description
BLS7G2325L-105
-
flanged LDMOST ceramic package; 2 mounting holes;
2 leads
Version
SOT502A
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
I
D
T
stg
T
j
Parameter
drain-source voltage
gate-source voltage
drain current
storage temperature
junction temperature
Conditions
Min
-
0.5
-
65
-
Max
65
+13
28
+150
200
Unit
V
V
A
C
C
5. Thermal characteristics
Table 5.
Symbol
R
th(j-c)
Thermal characteristics
Parameter
thermal resistance from junction to case
Conditions
T
case
= 80
C;
P
L
= 100 W
Typ
0.3
Unit
K/W
BLS7G2325L-105
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 19 July 2011
2 of 9
NXP Semiconductors
BLS7G2325L-105
Power LDMOS transistor
6. Characteristics
Table 6.
Characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
Conditions
V
GS
= 0 V; I
D
= 1 mA
V
DS
= 10 V; I
D
= 150 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 5.35 A
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 5.25 A
Min
65
1.5
-
Typ
-
1.8
-
Max Unit
-
2.3
5
-
500
-
V
V
A
A
nA
S
25.1 29
-
-
-
-
0.1
10.5 -
7. Test information
Remark:
All testing performed in a class-AB production test circuit.
Table 7.
Functional test information
Mode of operation: 1-carrier N-CDMA, single carrier IS-95 with pilot, paging, sync and 6 traffic
channels (Walsh codes 8 - 13). PAR = 9.7 dB at 0.01 % probability on the CCDF, channel bandwidth
is 1.2288 MHz; f
1
= 2300 MHz; f
2
= 2500 MHz; RF performance at V
DS
= 28 V; I
Dq
= 900 mA;
T
case
= 25
C; unless otherwise specified.
Symbol
P
L(AV)
G
p
RL
in
D
ACPR
885k
Parameter
average output power
power gain
input return loss
drain efficiency
adjacent channel power ratio (885 kHz)
Conditions
Min Typ Max Unit
-
-
22
-
20
-
-
-
W
dB
dB
%
dBc
17.3 18
27
10
-
46 40
7.1 Ruggedness in class-AB operation
The BLS7G2325L-105 is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions: V
DS
= 28 V;
I
Dq
= 900 mA; P
L
= 100 W (CW); f = 2300 MHz.
BLS7G2325L-105
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 19 July 2011
3 of 9
NXP Semiconductors
BLS7G2325L-105
Power LDMOS transistor
7.2 Pulsed CW
20
G
p
(dB)
19
(2)
001aan765
60
η
D
(%)
001aan766
(3)
50
(1)
(2)
(3)
40
18
(1)
30
17
20
16
0
40
80
120
P
L
(W)
160
10
0
40
80
120
P
L
(W)
160
V
DS
= 28 V; I
Dq
= 900 mA.
(1) f = 2300 MHz
(2) f = 2400 MHz
(3) f = 2500 MHz
V
DS
= 28 V; I
Dq
= 900 mA.
(1) f = 2300 MHz
(2) f = 2400 MHz
(3) f = 2500 MHz
Fig 1.
Pulsed CW power gain as a function of load
power; typical values
Fig 2.
Pulsed CW drain efficiency as a function of
load power; typical values
7.3 CW
20
G
p
(dB)
19
40
001aan767
60
η
D
(%)
001aan768
(3)
50
(1)
(2)
(3)
(2)
18
(1)
30
17
20
16
0
40
80
120
P
L
(W)
160
10
0
40
80
120
P
L
(W)
160
V
DS
= 28 V; I
Dq
= 900 mA.
(1) f = 2300 MHz
(2) f = 2400 MHz
(3) f = 2500 MHz
V
DS
= 28 V; I
Dq
= 900 mA.
(1) f = 2300 MHz
(2) f = 2400 MHz
(3) f = 2500 MHz
Fig 3.
CW power gain as a function of load power;
typical values
Fig 4.
CW drain efficiency as a function of load
power; typical values
© NXP B.V. 2011. All rights reserved.
BLS7G2325L-105
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 2 — 19 July 2011
4 of 9
NXP Semiconductors
BLS7G2325L-105
Power LDMOS transistor
8. Package outline
Flanged LDMOST ceramic package; 2 mounting holes; 2 leads
SOT502A
D
A
3
D1
F
U1
q
C
B
c
1
L
H
U2
p
w1
M
A
M
B
M
E1
E
A
2
b
w2
M
C
M
Q
0
5
scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
mm
inches
A
4.72
3.43
0.186
0.135
b
12.83
12.57
c
0.15
0.08
D
D1
E
9.50
9.30
E1
9.53
9.25
F
1.14
0.89
H
19.94
18.92
L
5.33
4.32
p
3.38
3.12
Q
1.70
1.45
q
27.94
U1
34.16
33.91
1.345
1.335
U2
9.91
9.65
0.390
0.380
w1
0.25
0.01
w2
0.51
0.02
20.02 19.96
19.61 19.66
0.788 0.786
0.772 0.774
0.505 0.006
0.495 0.003
0.374 0.375
0.366 0.364
0.045 0.785
0.035 0.745
0.210 0.133
0.170 0.123
0.067
1.100
0.057
OUTLINE
VERSION
SOT502A
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-28
03-01-10
Fig 5.
Package outline SOT502A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
BLS7G2325L-105
Product data sheet
Rev. 2 — 19 July 2011
5 of 9
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