White Electronic Designs
WV3EG64M72ETSU-D3
PRELIMINARY*
512MB – 64Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
• V
CC
= V
CCQ
= +2.5V ±0.2V
184 pin DIMM package
• D3 PCB height: 28.58mm (1.125")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The WV3EG64M72ETSU is a 64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
October 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WV3EG64M72ETSU-D3
PRELIMINARY
PIN CONFIGURATION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SYMBOL
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
CC
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
CCQ
CK1
CK1#
V
SS
DQ10
DQ11
CKE0
V
CCQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
CCQ
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
CC
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
CC
PIN
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
SYMBOL
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
CCQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
CCQ
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
V
CC
NC
DQ48
DQ49
V
SS
CK2#
CK2
V
CCQ
DQS6
DQ50
DQ51
V
SS
V
CCID
DQ56
DQ57
V
CC
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
SYMBOL
V
SS
DQ4
DQ5
V
CCQ
DM0
DQ6
DQ7
V
SS
NC
NC
NC
V
CCQ
DQ12
DQ13
DM1
V
CC
DQ14
DQ15
NC
V
CCQ
NC
DQ20
A12
V
SS
DQ21
A11
DM2
V
CC
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
CCQ
DM3
A3
DQ30
V
SS
DQ31
CB4
CB5
V
CCQ
CK0
CK0#
PIN
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
SYMBOL
V
SS
DM8
A10
CB6
V
CCQ
CB7
V
SS
DQ36
DQ37
V
CC
DM4
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
CCQ
CS0#
NC
DM5
V
SS
DQ46
DQ47
NC
V
CCQ
DQ52
DQ53
NC
V
CC
DM6
DQ54
DQ55
V
CCQ
NC
DQ60
DQ61
V
SS
DM7
DQ62
DQ63
V
CCQ
SA0
SA1
SA2
V
CCSPD
A0-A12
BA0-BA1
DQ0-DQ63
DQS0-DQS8
CB0-CB7
CK0, CK1, CK2
CK0#, CK1#, CK2#
CKE0
CS0#
RAS#
CAS#
WE#
DM0-DM8
V
CC
V
CCQ
V
SS
V
REF
V
CCSPD
SDA
SCL
SA0-SA2
V
CCID
NC
PIN NAMES
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Check Bits
Clock Input
Clock Input
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-in-mask
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
Serial clock
Address in EEPROM
V
CC
Indentification Flag
No Connect
October 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WV3EG64M72ETSU-D3
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DM0
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
*Clock Net Wiring
DRAM 1
1.5PF
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
R = 120 Ohm
Card
Edge
DRAM 3
1.5PF
DRAM 5
1.5PF
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
Clock Wiring
Clock
Input
CK0, CK0#
CK1, CK1#
CK2, CK2#
SERIAL PD
DDR SDRAMs
2 DDR SDRAMs
3 DDR SDRAMs
3 DDR SDRAMs
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
WE#
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
NOTE: All datalines are terminated through a 22 ohm series resistor.
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown.
October 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WV3EG64M72ETSU-D3
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Voltage on V
CCQ
supply relative to V
SS
Storage Temperature
Operating Temperature
Power Dissipation
Short Circuit Current
Symbol
V
IN
, V
OUT
V
CC
V
CCQ
T
STG
T
A
P
D
I
OS
Value
-0.5 to 3.6
-1.0 to 3.6
-1.0 to 3.6
-55 to +150
0 to +70
9
50
Units
V
V
V
°C
°C
W
mA
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C
Parameter
Supply voltage DDR266/DDR333 (nominal V
CC
of 2.5V)
I/O Supply voltage DDR266/DDR333 (nominal V
CC
of 2.5V)
I/O Reference voltage
I/O Termination voltage
Input logic high voltage
Input logic low voltage
Input voltage level, CK and CK#
Input differential voltage, CK and CK#
Input crossing point voltage, CK and CK#
Addr, CAS#,
RAS#, WE#
CS#, CKE
CK, CK#
DM
T
A
70°C, V
CC
= V
CCQ
= 2.5V ± 0.2V
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
V
IX
(DC)
Min
2.3
2.3
0.49*V
CCQ
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.36
0.3
-18
-18
-6
-2
-5
-16.8
16.8
-9
9
Max
2.7
2.7
0.51*V
CCQ
V
REF
+0.04
V
CCQ
+0.30
V
REF
-0.15
V
CCQ
+0.30
V
CCQ
+0.60
V
CCQ
+0.60
18
18
6
2
5
—
—
—
—
Unit
V
V
V
V
V
V
V
V
uA
uA
uA
uA
uA
mA
mA
mA
mA
Note
1
2
3
Input leakage current
I
I
Output leakage current
Output high current (normal strengh); V
OUT
= V +0.84V
Output high current (normal strengh); V
OUT
= V
TT
-0.84V
Output high current (half strengh); V
OUT
= V
TT
+0.45V
Output high current (half strengh); V
OUT
= V
TT
-0.45V
I
OZ
I
OH
I
OL
I
OH
I
OL
NOTES:
1. V
REF
is expected to be equal to 0.5*V
CCQ
of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on V
REF
may not exceed ±2% of the DC
value
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK#.
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= V
CCQ
= 2.5V
Parameter
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CS0#)
Input Capacitance (CK0 to CK2, CK0# to CK2#)
Input Capacitance (DM0-DM7)
Data and DQS input/output capacitance (DQ0-DQ63)
October 2005
Rev. 0
4
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
OUT1
Min
22
22
22
10
8
8
Max
31
31
31
13
9
9
Unit
pF
pF
pF
pF
pF
pF
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
0°C T
A
70°C, V
CC
= V
CCQ
= 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol
Conditions
WV3EG64M72ETSU-D3
PRELIMINARY
I
DD
SPECIFICATIONS AND TEST CONDITIONS
DDR333 @
CL = 2.5
945
1215
45
270
270
405
1260
1350
1845
45
3240
Unit
Operating current
Operating current
Percharge power-
down standby current
Idle standby current
Active power-down
standby current
Active standby
current
Operating current
Operating current
Auto refresh current
Self refresh current
Orerating current
I
DD0*
I
DD1*
I
DD2P**
I
DD2F**
I
DD3P**
I
DD3N**
I
DD4R*
I
DD4W*
I
DD5**
I
DD6**
I
DD7*
One device bank active; Active-Precharge; t
RC
= t
RC(MIN)
; t
CK
= t
CK(MIN)
;
DQ, DM and DQS inputs change once per clock cycle; Address and control
inputs change once every two clock cycles
One device bank; Active-Read-Precharge; BL = 4; t
RC
= t
RC(MIN)
; t
CK
= t
CK(MIN)
;
I
OUT
= 0mA; Address and control inputs change once per clock cycle
All device banks are idle; Power-down mode; t
CK
= t
CK(MIN)
; CKE = LOW
CS# = HIGH; All device banks are idle; t
CK
= t
CK(MIN)
; CKE = HIGH; Address
and other control inputs changing once per clock cycle. V
IN
= V
REF
for DQ,
DQS and DM
One device bank active; Power-down mode; t
CK
= t
CK(MIN)
; CKE = LOW
CS# = HIGH; CKE = HIGH; One device bank active; t
RC
= t
RAS(MAX)
;
t
CK
= t
CK(MIN)
; DQ, DM and DQS inputs change twice per clock cycle; Address
and other control inputs changing once per clock cycle
Burst = 2; Reads; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; t
CK
= t
CK(MIN)
; I
OUT
= 0mA
Burst = 2; Writes; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; t
CK
= t
CK(MIN)
; DQ, DM and
DQS inputs change twice per clock cycle
t
RC
= t
RFC(MIN)
CKE < 0.2V
Four device bank interleaving Reads Burst = 4 with auto precharge;
t
RC
= t
RFC(MIN)
; t
CK
= t
CK(MIN)
; Address and control inputs change only during
Active READ, or WRITE commands
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note: These specifications apply to modules built with
Samsung
components only.
* Value calculated as one module rank in this operation condition and other module rank in I
DD2P
(CKE low) mode.
** Value calculated as all module ranks in this operation condition.
October 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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