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GS8342Q36AGE-250IT: 产品描述DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; 产品类别存储存储; 文件大小498KB，共34页; 制造商GSI Technology; 官网地址http://www.gsitechnology.com/; 标准

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GS8342Q36AGE-250IT概述

DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8342Q36AGE-250IT规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	GSI Technology
零件包装代码	BGA
包装说明	BGA,
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.B
最长访问时间	0.45 ns
其他特性	PIPELINED ARCHITECTURE
JESD-30 代码	R-PBGA-B165
JESD-609代码	e1
长度	17 mm
内存密度	37748736 bit
内存集成电路类型	DDR SRAM
内存宽度	36
湿度敏感等级	3
功能数量	1
端子数量	165
字数	1048576 words
字数代码	1000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	1MX36
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	1.5 mm
最大供电电压 (Vsup)	1.95 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	15 mm

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GS8342Q08/09/18/36AE-278/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write (x36, x18, and x9) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

and 144Mb devices

36Mb SigmaQuad-II

Burst of 2 SRAM

Clocking and Addressing Schemes

167 MHz–278 MHz

1.8 V V

1.8 V and 1.5 V I/O

The GS8342Q08/09/18/36AE SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock quasi independently with the C and C

clock inputs. C and C are also independent single-ended clock

inputs, not differential inputs. If the C clocks are tied high, the

K clocks are routed internally to fire the output registers

instead.

Each internal read and write operation in a SigmaQuad-II B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaQuad-II B2 RAM is always one address pin less than the

advertised index depth (e.g., the 4M x 8 has a 2M addressable

index).

SigmaQuad™ Family Overview

The GS8342Q08/09/18/36AE are built in compliance with

the SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342Q08/09/18/36AE SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Parameter Synopsis

-278

tKHKH

tKHQV

3.6 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

Rev: 1.06c 11/2011

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342Q36AGE-250IT

GS8342Q36AGE-250IT概述

GS8342Q36AGE-250IT规格参数

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