Specifications for Rad Hard QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD numbers
listed below must be used when ordering.
Detailed Electrical Specifications for the HS-303ARH,
HS-303AEH, HS-303BRH, HS-303BEH are contained in
SMD
5962-95813.
A “hot-link” is provided from our website for
downloading
Functional Diagram
IN
N
P
D
Pin Configurations
HS1-303ARH, HS-303BRH
(SBDIP), CDIP2-T14
TOP VIEW
NC
S3
D3
D1
1
2
3
4
5
6
7
14 V+
13 S4
12 D4
11 D2
10 S2
9 IN2
8 V-
TRUTH TABLE
LOGIC
0
1
SW1 AND SW2
OFF
ON
SW3 AND SW4
ON
OFF
S1
IN1
GND
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
(FLATPACK) CDFP3-F14
TOP VIEW
1
NC
S3
D3
D1
S1
IN1
GND
3
4
5
6
7
12
11
10
9
8
2
14
13
V+
S4
D4
D2
S2
IN2
V-
December 12, 2012
FN6411.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2006, 2008, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ordering Information
ORDERING NUMBER
(Note)
5962F9581304QCC
5962F9581304QXC
5962F9581304V9A
5962F9581306V9A
5962F9581304VCC
5962F9581306VCC
5962F9581304VXC
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
5962F9581306VXC
5962F9581305QCC
5962F9581305QXC
5962F9581305V9A
5962F9581307V9A
5962F9581305VCC
5962F9581307VCC
5962F9581305VXC
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
5962F9581307VXC
PART NUMBER
HS1-303ARH-8
HS9-303ARH-8
HS0-303ARH-Q
HS0-303AEH-Q
HS1-303ARH-Q
HS1-303AEH-Q
HS9-303ARH-Q
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
HS9-303AEH-Q
HS1-303BRH-8
HS9-303BRH-8
HS0-303BRH-Q
HS0-303BEH-Q
HS1-303BRH-Q
HS1-303BEH-Q
HS9-303BRH-Q
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
HS9-303BEH-Q
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
14 LD SBDIP
14 LD Flatpack
14 LD Flatpack
D14.3
K14.A
K14.A
14 LD SBDIP
14 LD Flatpack
14 LD Flatpack
14 LD SBDIP
14 LD Flatpack
14 LD SBDIP
14 LD SBDIP
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
D14.3
K14.A
K14.A
D14.3
K14.A
D14.3
D14.3
D14.3
D14.3
K14.A
14 LD SBDIP
14 LD Flatpack
14 Ld SBDIP
14 Ld SBDIP
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
PKG.
PKG.
DWG. #
D14.3
K14.A
D14.3
D14.3
D14.3
D14.3
K14.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
2
FN6411.2
December 12, 2012
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Die Characteristics
DIE DIMENSIONS:
2690µm x 5200µm (106mils x 205mils)
Thickness: 483µm
±
25.4µm (19mils
±
1mil)
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0k
Å
±
1.0k
Å
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
Å
±
2k
Å
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
196
Metallization Mask Layout
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
IN2
V-
V+
GND
IN1
D4
D2
S4
S2
S1
S3
For additional products, see
www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at
www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
3
D3
D1
FN6411.2
December 12, 2012
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
-D-
BASE
METAL
b1
M
(b)
SECTION A-A
(c)
LEAD FINISH
D14.3
MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
SYMBOL
A
b
b1
b2
MIN
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.220
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MILLIMETERS
MIN
-
0.36
0.36
1.14
0.58
0.20
0.20
-
5.59
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
2.54 BSC
7.62 BSC
3.81 BSC
3.18
0.38
0.13
0.13
90
o
-
-
-
-
14
5.08
1.52
-
-
105
o
0.38
0.76
0.25
0.038
NOTES
-
2
3
-
4
2
3
-
-
-
-
-
-
5
6
7
-
-
-
-
2
8
Rev. 0 4/94
E
M
-B-
bbb S
C A-B S
D
BASE
PLANE
SEATING
PLANE
S1
b2
b
ccc M C A - B S
A A
S2
-C-
Q
A
L
D S
b3
c
c1
e
A
e
D S
D
E
e
A/2
c
e
eA
eA/2
0.100 BSC
0.300 BSC
0.150 BSC
0.125
0.015
0.005
0.005
90
o
-
-
-
-
14
0.200
0.060
-
-
105
o
0.015
0.030
0.010
0.0015
aaa
M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark.
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b2.
5. Dimension Q shall be measured from the seating plane to the base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the nearest
metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
L
Q
S1
S2
α
aaa
bbb
ccc
M
N
4
FN6411.2
December 12, 2012
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
A
K14.A
MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES
SYMBOL
MIN
0.045
0.015
0.015
0.004
0.004
-
0.235
-
0.125
0.030
0.050 BSC
0.008
0.270
0.026
0.005
-
14
0.015
0.370
0.045
-
0.0015
0.20
6.86
0.66
0.13
-
14
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
-
MILLIMETERS
MIN
1.14
0.38
0.38
0.10
0.10
-
5.97
-
3.18
0.76
1.27 BSC
0.38
9.40
1.14
-
0.04
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
-
NOTES
-
-
-
-
-
3
-
3
-
7
-
2
-
8
6
-
-
Rev. 0 5/18/94
e
PIN NO. 1
ID AREA
A
-A-
-B-
D
A
b
S1
b
E1
b1
c
c1
D
0.004
Q
A
-C-
M H A-B S
D S
E
0.036
M H A-B S
C
-D-
D S
E
E1
E2
-H-
L
E3
E2
E3
LEAD FINISH
L
E3
e
k
L
SEATING AND
BASE PLANE
c1
BASE
METAL
b1
M
M
(b)
SECTION A-A
(c)
Q
S1
M
N
NOTES:
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark. Alternately, a tab (dimension k) may be used to identify
pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of
dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M ap-
plies to lead plating and finish thickness. The maximum limits of lead
dimensions b and c or M shall be measured at the centroid of the fin-
ished lead surfaces, when solder dip or tin plate lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the menis-
cus) of the lead from the body. Dimension Q minimum shall be reduced
by 0.0015 inch (0.038mm) maximum when solder dip lead finish is
applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
在全球半导体产业因景气不佳而纷传并购、整合之际，两大IT巨头三星、IBM日前却双双宣布，将强化半导体产业投资。 三星电子本周一宣布，已向韩国证券交易所提交一份申请文件，打算2008年投下10.5亿美元，用于升级内存芯片生产线、改进技术工艺，从而提高产能并降低成本。无独有偶。本周二IBM公司宣布，未来3年将投资10亿美元，用于扩充位于纽约州 East Fishkill 的半导体工厂，以消...[详细]
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
