10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821APW | 74LVC821ABQ | 74LVC821AD | 74LVC821ADB | 74LVC821A_2 | 74LVC821A_3 | 74LVC821A_1 | |
---|---|---|---|---|---|---|---|
描述 | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state |
电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved