74AUP1G98 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate
October 2010
74AUP1G98
TinyLogic
®
Low Power Universal Configurable
Two-Input Logic Gate
Features
0.8V to 3.6V V
CC
Supply Operation
3.6V Over-Voltage Tolerant I/Os at V
CC
from 0.8V to 3.6V
High Speed t
PD
- 3.0ns: Typical at 3.3V
Power-Off High-Impedance Inputs and Outputs
Low Static Power Consumption
- I
CC
=0.9µA Maximum
Low Dynamic Power Consumption
- C
PD
=2.5pF Typical at 3.3V
Ultra-Small MicroPak™ Packages
Description
The 74AUP1G98 is a universal configurable 2-input
logic gate that provides a high performance and low
power solution ideal for battery-powered portable
applications. This product is designed for a wide low
voltage operating range (0.8V to 3.6V) and guarantees
very low static and dynamic power consumption across
the entire voltage range. All inputs are implemented with
hysteresis to allow for slower transition input signals and
better switching noise immunity.
The 74AUP1G98 provides for multiple functions as
determined by various configurations of the three inputs.
The potential logic functions provided are MUX, AND,
OR, NAND, and NOR, inverter and buffer. Refer to
Figures 5 to 11.
Ordering Information
Part Number
74AUP1G98L6X
74AUP1G98FHX
Top Mark
AE
AE
Package
6-Lead Micropak™, 1.0mm Wide
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Packing Method
5000 Units on
Tape & Reel
5000 Units on
Tape & Reel
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
74AUP1G98 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate
Logic Diagram
3
4
Y
A
B
1
C
6
Figure 1. Logic Diagram (Positive Logic)
Pin Configurations
B
GND
A
1
2
3
6
5
4
C
V
CC
Y
Figure 2. MicroPak™ (Top Through View)
Pin Definitions
Pin # MicroPak™
1
2
3
4
5
6
Name
B
GND
A
Y
V
CC
C
Data Input
Ground
Data Input
Output
Description
Supply Voltage
Data Input
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
2
74AUP1G98 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate
Function Table
Inputs
C
L
L
L
L
H
H
H
H
74AUP1G98
A
L
H
L
H
L
H
L
H
B
L
L
H
H
L
L
H
H
Y=Output
H
H
L
L
H
L
H
L
H = HIGH Logic Level
L = LOW Logic Level
Function Selection Table
2-Input Logic Function
2-to-1 MUX with Inverted Output
2-Input NAND Gate
2-Input NOR Gate with One Inverted Input
2-Input AND Gate with One Inverted Input
2-Input NAND Gate with One Inverted Input
2-Input OR Gate with One Inverted Input
2-Input NOR Gate
Buffer
Inverter
Connection Configuration
Figure 3
Figure 4
Figure 5
Figure 5
Figure 6
Figure 6
Figure 7
Figure 8
Figure 9
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
3
74AUP1G98 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate
74AUP1G98 Logic Configurations
Figure 3 through Figure 9 show the logical functions that
can be implemented using the 74AUP1G98. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
implementation is next to the board-level physical
implementation of how the pins of the function should be
connected.
V
CC
C
B
A
GND
B
Y
A
1
2
3
6
5
4
Y
C
C
A
Y
A
GND
1
2
3
6
5
4
Y
C
V
CC
Note:
1. When C is L, Y=B.
2. When C is H, Y=A.
Figure 3. 2-to-1 MUX with Inverted Output
Figure 4.
2-Input NAND Gate
V
CC
C
A
C
A
C
V
CC
B
Y
B
C
B
Y
1
2
3
6
5
4
Y
C
Y
1
2
Y
GND
A
3
6
5
4
Y
C
GND
Figure 5.
Input NOR Gate with One Inverted Input Figure 6.
2-Input AND Gate with One Inverted Input
2-Input NAND Gate with One Inverted Input
2-Input OR Gate with One Inverted Input
V
CC
V
CC
C
B
Y
B
1
2
3
6
5
4
C
Y
C
Y
1
2
3
6
5
4
C
Y
GND
GND
Figure 7. 2-Input NOR Gate
Figure 8.
V
CC
Buffer
B
Y
B
1
2
3
6
5
4
Y
GND
Figure 9.
Inverter
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
4
74AUP1G98 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OH
/ I
OL
I
CC
or I
GND
T
STG
T
J
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
Parameter
Min.
-0.5
-0.5
Max.
4.6
4.6
V
CC
+ 0.5
4.6
-50
-50
+50
±50
±50
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C
mW
HIGH or LOW State
V
CC
=0V
V
IN
< 0V
V
OUT
< 0V
V
OUT
> V
CC
(3)
-0.5
-0.5
DC Output Source / Sink Current
DC V
CC
or Ground Current per Supply Pin
Storage Temperature Range
Junction Temperature Under Bias
Junction Lead Temperature, Soldering 10s
Power Dissipation at +85°C
MicroPak-6
MicroPak2-6
-65
+150
+150
+260
130
120
5000+
2000
ESD
Human Body Model, JEDEC:JESD22-A114
Charged Device Model, JEDEC:JESD22-C101
V
Note:
3. I
O
absolute maximum rating must be observed.
Recommended Operating Conditions
(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
V
OUT
Parameter
Supply Voltage
Input Voltage
Output Voltage
V
CC
=0V
Conditions
Min.
0.8
0
0
0
Max.
3.6
3.6
3.6
V
CC
±4.0
±3.1
±1.9
±1.7
±1.1
±20.0
Unit
V
V
V
HIGH or LOW State
V
CC
=3.0V to 3.6V
V
CC
=2.3V to 2.7V
V
CC
=1.65V to 1.95V
V
CC
=1.4V to 1.6V
V
CC
=1.1V to 1.3V
V
CC
=0.8V
I
OH
/I
OL
Output Current
mA
µA
°C
T
A
Operating Temperature, Free Air
Thermal Resistance
MicroPak-6
MicroPak2-6
-40
+85
500
560
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
5
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