74AUP1G96 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
September 2012
74AUP1G96
TinyLogic
®
Low Power Universal Configurable
Two-Input Logic Gate (Open Drain Output)
Features
0.8 V to 3.6V V
CC
Supply Operation
3.6 V Over-Voltage Tolerant I/Os at V
CC
from 0.8 V to 3.6 V
Extremely High Speed t
PD
- 3.2 ns: Typical at 3.3 V
Power-Off High-Impedance Inputs and Outputs
Low Static Power Consumption
- I
CC
=0.9 µA Maximum
Low Dynamic Power Consumption
- C
PD
=3.0 pF Typical at 3.3 V
Ultra-Small MicroPak™ Packages
Description
The 74AUP1G96 is a universal configurable. two-input
logic gate with an open-drain output that provides a
high-performance and low-power solution for battery-
powered portable applications. This product is
designed for a wide low voltage operating range (0.8 V
to 3.6 V) and guarantees very low static and dynamic
power consumption across the entire voltage range. All
inputs are implemented with hysteresis to allow for
slower transition input signals and better switching
noise immunity.
The 74AUP1G96 provides for multiple functions as
determined by various configurations of the three inputs.
The potential logic functions provided are MUX, AND,
OR, NAND, and, NOR inverter and buffer (see
Figure 2
to Figure 8).
Ordering Information
Part Number
74AUP1G96L6X
74AUP1G96FHX
Top Mark
AP
AP
Package
6-Lead, MicroPak™ 1.0 x 1.45mm, JEDEC MO-252
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Packing Method
5000 Units on
Tape & Reel
5000 Units on
Tape & Reel
© 2008 Fairchild Semiconductor Corporation
74AUP1G96 • Rev. 1.0.1
www.fairchildsemi.com
74AUP1G96 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Pin Configurations
B
GND
A
1
2
3
6
5
4
C
V
CC
Y
Figure 1. MicroPak™ (Top Through View)
Pin Definitions
Pin #
1
2
3
4
5
6
Name
B
GND
A
Y
V
CC
C
Description
Data Input
Ground
Data Input
Output (Open Drain)
Supply Voltage
Data Input
Function Table
Inputs
C
L
L
L
L
H
H
H
H
Y=Output
A
L
H
L
H
L
H
L
H
H
(1)
H
(1)
L
L
H
(1)
L
H
(1)
L
B
L
L
H
H
L
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
Note:
1. High impedance output state, open drain.
2-Input Logic Function
2-to-1 MUX with Inverted Output
2-Input NAND Gate
2-Input NOR Gate with One Inverted Input
2-Input AND Gate with One Inverted Input
2-Input NAND Gate with One Inverted Input
2-Input OR Gate with One Inverted Input
2-Input NOR Gate
Buffer
Inverter
© 2008 Fairchild Semiconductor Corporation
74AUP1G96 • Rev 1.0.1
Connection Configuration
Figure 2
Figure 3
Figure 4
Figure 4
Figure 5
Figure 5
Figure 6
Figure 7
Figure 8
www.fairchildsemi.com
2
74AUP1G96 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Logic Configurations
Figure 2 through Figure 8 show the logical functions that
can be implemented using the 74AUP1G98. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
implementation is next to the board-level physical
implementation of how the pins of the function should be
connected.
V
CC
C
B
B
A
GND
Y
A
1
2
3
6
5
4
Y
C
C
A
A
GND
Y
1
2
3
6
5
4
Y
C
V
CC
Note:
2. When C is L, Y=B.
3. When C is H, Y=A.
Figure 2. 2-to-1 MUX with Inverted Output
Figure 3. 2-Input NAND Gate
V
CC
C
A
1
C
A
GND
2
Y
A
3
6
5
4
Y
GND
C
Y
B
1
2
3
6
5
4
Y
C
V
CC
Y
C
B
C
B
Y
Figure 4. Input NOR Gate with One Inverted Input
2-Input AND Gate with One Inverted Input
Figure 5. 2-Input NAND Gate with One Inverted Input
2-Input OR Gate with One Inverted Input
V
CC
V
CC
C
B
Y
B
1
2
3
6
5
4
C
Y
C
Y
1
2
3
6
5
4
C
Y
GND
GND
Figure 6. 2-Input NOR Gate
Figure 7. Buffer
V
CC
B
Y
B
1
2
3
6
5
4
Y
GND
Figure 8. Inverter
© 2008 Fairchild Semiconductor Corporation
74AUP1G96 • Rev 1.0.1
www.fairchildsemi.com
3
74AUP1G96 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT(2)
I
IK
I
OK
I
OL
I
CC
or I
GND
T
STG
T
J
T
L
P
D
ESD
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
Parameter
Min.
-0.5
-0.5
-0.5
Max.
4.6
4.6
4.6
-50
-50
+50
±50
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C
mW
V
V
IN
< 0 V
V
OUT
< 0 V
DC V
CC
or Ground Current per Supply Pin
Storage Temperature Range
Junction Temperature Under Bias
Junction Lead Temperature, Soldering 10s
Power Dissipation at +85°C
MicroPak-6™
MicroPak2™-6
Human Body Model, JEDEC:JESD22-A114
Charged Device Model, JEDEC:JESD22-C101
-65
+150
+150
+260
130
120
4000
2000
Note:
2. I
O
absolute maximum rating must be observed.
Recommended Operating Conditions
(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
V
OUT
Parameter
Supply Voltage
Input Voltage
Output Voltage
Condition
Min.
0.8
0
0
Max.
3.6
3.6
3.6
±4.0
±3.1
±1.9
±1.7
±1.1
±20.0
Unit
V
V
V
V
CC
=3.0 V to 3.6 V
V
CC
=2.3 V to 2.7 V
I
OL
Output Current
V
CC
=1.65 V to 1.95 V
V
CC
=1.4 V to 1.6 V
V
CC
=1.1 V to 1.3 V
V
CC
=0.8 V
T
A
θ
JA
Operating Temperature, Free Air
Thermal Resistance
MicroPak-6™
MicroPak2™-6
-40
mA
µA
°C
°C/W
+85
500
560
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
© 2008 Fairchild Semiconductor Corporation
74AUP1G96 • Rev. 1.0.1
www.fairchildsemi.com
4
74AUP1G96 — TinyLogic
®
Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
DC Electrical Characteristics
Symbol
Parameter
V
CC
0.80
1.10
V
P
Positive
Threshold
Voltage
1.40
1.65
2.30
3.00
0.80
1.10
V
N
Negative
Threshold
Voltage
1.40
1.65
2.30
3.00
0.80
1.10
V
H
Hysteresis
Voltage
1.40
1.65
2.30
3.00
0.80
≤
V
CC
≤
3.60 I
OL
=20 µA
1.10
≤
V
CC
≤
1.30 I
OL
=1.1 mA
1.40
≤
V
CC
≤
1.60 I
OL
=1.7 mA
V
OL
LOW Level
1.65
≤
V
CC
≤
1.95 I
OL
=1.9 mA
Output Voltage
2.30
≤
V
CC
≤
2.70 I
OL
=3.1 mA
2.70
≤
V
CC
≤
3.60 I
OL
=4.0 mA
I
IN
I
OFF
Input Leakage
Current
Power Off
Leakage
Current
Additional
Power Off
Leakage
Current
Quiescent
Supply Current
Increase in I
CC
per Input
0 V to 3.6 V
0V
0
≤
V
IN
≤
3.6 V
0
≤
(V
IN
, V
O
)
≤
3.6 V
V
IN
or V
O
=0 V
to 3.6 V
V
IN
- V
CC
or GND
V
CC
≤
V
IN
≤
3.6 V
V
IN
=V
CC
-0.6 V
40.0
Condition
T
A
=25°C
Min.
0.30
0.53
0.74
0.91
1.37
1.88
0.10
0.26
0.39
0.47
0.69
0.88
0.07
0.08
0.18
0.27
0.53
0.79
T
A
=-40 to 85°C
Min.
0.30
0.53
0.74
0.91
1.37
1.88
0.10
0.26
0.39
0.47
0.69
0.88
0.07
0.08
0.18
0.27
0.53
0.79
Max.
0.60
0.90
1.11
1.29
1.77
2.29
0.60
0.65
0.75
0.84
1.04
1.24
0.50
0.46
0.56
0.66
0.92
1.31
0.10
0.30 x
V
CC
0.31
0.31
0.44
0.44
±0.1
0.2
Max.
0.60
0.90
1.11
1.29
1.77
2.29
0.60
0.65
0.75
0.84
1.04
1.24
0.50
0.46
0.56
0.66
0.92
1.31
0.10
0.30 x
V
CC
0.37
0.35
0.45
0.45
±0.5
0.6
Unit
V
V
V
V
µA
µA
ΔI
OFF
0 V to 0.2 V
0.2
0.5
0.6
0.9
±0.9
50.0
µA
I
CC
ΔI
CC
0.8 V to 3.6 V
3.3 V
µA
µA
© 2008 Fairchild Semiconductor Corporation
74AUP1G96 • Rev. 1.0.1
www.fairchildsemi.com
5
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