2M x 8 - Bit Dynamic RAM
2k Refresh
(Hyper Page Mode- EDO)
Advanced Information
•
•
•
HYB3117805BSJ -50/-60/-70
2 097 152 words by 8-bit organization
0 to 70 °C operating temperature
Performance:
-50
tRAC
tCAC
tAA
tRC
tHPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Hyper page mode (EDO)
cycle time
50
13
25
84
20
-60
60
15
30
104
25
-70
70
20
35
124
30
ns
ns
ns
ns
ns
•
•
Single + 3.3 V (± 0.3 V) supply
Low power dissipation
max. 432 mW active (-50 version)
max. 396 mW active (-60 version)
max. 360 mW active (-70 version)
7.2 mW standby (LV-TTL)
3.6 mW standby (CMOS)
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
Hyper page mode (EDO) capability
All inputs, outputs and clocks fully TTL-compatible
2048 refresh cycles / 32 ms (2k-Refresh)
Plastic Package:
P-SOJ-28-3 400 mil
•
•
•
•
•
Semiconductor Group
1
1.96
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
The HYB 3117805BSJ is a 16 MBit dynamic RAM organized as 2 097 152 words by 8-bits. The HYB
3117805BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 3117805BSJ to be packaged in a standard
SOJ 28
plastic package with 400 mil width. These packages provide high system bit densities and are
compatible with commonly used automatic testing and insertion equipment. System-oriented
features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic
device families such as Schottky TTL.
Ordering Information
Type
HYB 3117805BJ-50
HYB 3117805BJ-60
HYB 3117805BJ-70
Pin Names
A0-A10
A0-A9
RAS
OE
I/O1-I/O8
CAS
WE
Row Address Inputs
Column Address Inputs
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply (+ 3.3 V)
Ground (0 V)
not connected
Ordering Code
Q67100-Q1151
Q67100-Q1152
Package
P-SOJ-28-3 400 mil
P-SOJ-28-3 400 mil
P-SOJ-28-3 400 mil
Descriptions
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
V
CC
V
SS
N.C.
Semiconductor Group
2
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
P-SOJ-28-3
400 mil
VCC
I/O1
I/O2
I/O3
I/O4
WE
RAS
N.C.
A10
A0
A1
A2
A3
VCC
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
Pin Configuration
Semiconductor Group
3
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
I/O1
I
/O2
I
/O8
WE
CAS
.
&
Data in
Buffer
No. 2 Clock
Generator
8
Data out
Buffer
8
OE
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
Column
Address
Buffer(10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
8
Refresh
Counter (11)
11
Row
1024
x8
Address
Buffers(11)
11
Decoder
2048
Row
Memory Array
2048x1024x8
RAS
No. 1 Clock
Generator
Block Diagram
Semiconductor Group
4
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage...................................................................................................-1.0V to 4.6 V
Power dissipation..................................................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
Input high voltage
Input low voltage
TTL Output high voltage (
I
OUT
= – 2 mA)
TTL Output low voltage (
I
OUT
= 2 mA)
CMOS Output high voltage (
I
OUT
= –100 uA)
CMOS Output low voltage (
I
OUT
= 100 uA)
Input leakage current
(0 V
≤
V
IH
≤
Vcc + 0.3V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
≤
V
OUT
≤
Vcc + 0.3V)
Average
V
CC
supply current:
-50 ns version
-60 ns version
-70 ns version
(RAS, CAS, address cycling,
t
RC
=
t
RC
min.)
Symbol
Limit Values
min.
max.
Vcc+0.5
0.8
–
0.4
0.2
10
10
2.0
– 0.5
2.4
–
–
– 10
– 10
Unit Test
Condition
V
V
V
V
V
V
µA
µA
1)
1)
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
VCC-0.2 –
–
–
–
120
110
100
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
(RAS cycling: CAS =
V
IH
,
t
RC
=
t
RC
min.)
–
–
–
–
2
120
110
100
mA
mA
mA
mA
–
2) 4)
2) 4)
2) 4)
I
CC3
Semiconductor Group
5
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