TSPC932
LOW VOLTAGE PLL CLOCK DRIVER
DESCRIPTION
The TSPC932 is a 3.3V compatible TTL based clock driver
device targetted for zero delay applications. The device pro-
vides 6 outputs for driving clock loads plus a single feedback
clock output. The dedicated feedback output gives the user six
choices of input multiplication factors: x1, x1.25, x1.5, x2, x2.5
and x3.
MAIN FEATURES
H
Vcc = 3.3V
5 %
H
MILITARY TEMPERATURE RANGE
H
PC603eT, TSPC740/750 and TSPC2605 COMPANION
H
SIX LOW SKEW OUTPUTS
H
ONE DEDICATED FEEDBACK OUTPUT
H
INDIVIDUAL OUTPUT ENABLE CONTROL
– All outputs can go into high impedance (3-state) for board
test purpose.
– Test Mode pin provided for low frequency testing.
H
FULLY INTEGRATED PLL
H
OUTPUT FREQUENCY UP TO 120MHz
H
SIX INPUT/OUTPUT RATIOS
TQFP 32
TD suffix
Thin Quad Flat Plastic package
Gullwing leads
SCREENING / QUALITY
This product is manufactured:
H
according to TCS upscreening standard.
LOGIC BLOCK DIAGRAM
PLL_EN
SD0:1
4
STOP
STOP
SD2
STOP
STOP
Q0
Q1
REF_CLK
FB_In
MODE
PLL
200–480MHz
4
2
5
6
Q2
Q3
MR/OE
COM_SD
SD3
SD4
STOP
STOP
SD5
QFB
FBSEL0
FBSEL1
Q4
Q5
May 1998
1/13
TSPC932
A. GENERAL DESCRIPTION
1. INTRODUCTION
The TSPC932 provides individual output enable control. The enables are synchronized to the internal clock such that upon assertion
the shut down signals will hold the clocks LOW without generating a runt pulse on the outputs. The shut down pins provide a means of
powering down certain portions of a system or a means of disabling outputs when the full compliment are not required for a specific
design. The shut down pins will disable the outputs when driven LOW. A common shut down pin is provided to disable all of the
outputs (except the feedback output) with a single control signal.
Two feedback select pins are provided to select the multiplication factor of the PLL. The TSPC932 provides six multiplication factors:
x1, x1.25, x1.5, x2, x2.5 and x3. In the 1.25 and 2.5 modes, The QFP output will not provide a 50% duty cycle. The phase detector of
the TSPC932 only monitor rising edge of its feedback signal, thus for this function a 50% duty cycle is not required. As the QFB signal
can also be used to drive other clocks in a system, it is important the user understands that the duty cycle will not be 50%. In the x1 and
x1.5 modes, QFB output will produce a 50% duty cycle signal.
The TSPC932 provides two pins for use in a system test and debug operations. The MR/OE input will force all of the outputs into a
high–impedance state for outputs back driving during system test. In addition, the PLL_EN pin allows user to bypass the PLL and to
drive directly through the REF_CLK input. Note that the REF_CLK signal will be routed through the dividers so that it will take several
transitions on the REF_CLK input to create a transition on outputs.
The TSPC932 is fully 3.3V compatible and requires no external loop filter components. All of the inputs are LVCMOS/LVTTL
compatible and the outputs produce rail–to–rail 3.3V swings. For series terminated application, each output can drive two series
terminated 50W transmission lines. For parallel terminated lines, the device can drive terminations of 50W into VCC/2. The device is
packaged in a 32–lead TQFP package to provide the optimum combination of performance, board density and cost.
2. PIN ASSIGNMENTS
GNDO
MODE
VCCA
SD0:1
VCCO
26
SD2
Q0
32
1
2
3
31
30
29
28
27
25
VCCI
REF_CLK
PLL_EN
FBSEL0
FBSEL1
MR/OE
COM_SD
GNDI
Pin 1 identifier
Q1
24
23
22
GNDO
Q2
VCCO
Q3
GNDO
TSPC932
4
5
6
7
8
21
TOP VIEW
(Not to Scale)
20
19
18
Q4
VCCO
Q5
17
9
10
11
12
13
14
15
16
Figure 1 : 32–Lead TQFP package pinout
2/13
VCCO_QFB
GND_QFB
SD4
SD3
FB_In
GNDA
QFB
SD5
TSPC932
3. SIGNALS DESCRIPTION
Pin
14, 18, 22, 26
32
1
8, 9, 16, 20, 24, 28
2
3
4, 5
6
7
10, 11, 12, 29, 30
13
15
17,19,21,23,25,27
31
Name
VCCO, VCCO_QFB
VCCA
VCCI
GNDO, GNDO_QFB,
GNDA, GNDI
REF_CLK
PLL_EN
FB_SEL[0;1]
MR/OE
COM_SD
SDx
FB_In
QFB
Qx
MODE
Function
Digital +3.3V Output Buffers Power Supply
Analog +3.3V PLL Power Supply
Digital +3.3V Core Power Supply
Ground
Reference Clock Input
PLL Enable
Outputs multiplication factor selection
Asserted: Outputs enable. Negated: Outputs in tri–state mode
Common outputs shut down
Individual outputs shut down
PLL Feedback Input
PLL Feedback Output
Clock Outputs
Outputs multiplication factor selection
3/13
TSPC932
B. DETAILED SPECIFICATIONS
1. SCOPE
This drawing describes the specific requirements for the microprocessor TSPC932, in compliance withTCS standard screening.
2. REQUIREMENTS
2.1. ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage
Input voltage
Input Current
Storage temperature range
Symbol
V
CC
V
in
I
IN
T
stg
Min
–0.3
–0.3
Max
4.6
V
CC
+ 0.3
20
Unit
V
V
mA
°C
–55
150
Note :
Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums
listed may affect device reliability or cause permanent damage to the device.
2.2.
Mechanical and environment
The microcircuits shall meet all environmental requirements of TCS standard screening.
2.3. Design and construction
The terminal connections shall be as shown in § A.2 PIN ASSIGNMENT
2.4. Marking
Each microcircuit are legible and permanently marked with the following information as minimum :
– Motorola initial marking including P/N and date–code
– XT label for TCS Extended Temperature Upscreening
2.5. Package
The precise case outlines are described at the end of this specification (§ 5. OUTLINES DIMENSIONS).
4/13
TSPC932
3. ELECTRICAL CHARACTERISTICS
3.1. DC CHARACTERISTICS
(TC = –55°C to 125°C, Vcc = 3.3V
5%)
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
Maximum Core Supply Current
Maximum PLL Supply Current
Maximum Output Buffers Supply Current
Input Capacitance
Output Capacitance
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
cc
I
CCPLL
I
CCO
C
IN
C
PD
Per output
25
15
I
OH
=–20mA (Note 1.)
I
OL
=+20mA (Note 1.)
Note 2.
2.4
0.5V
120
Comments
Min.
2.0
Typ.
Max.
3.6
0.8
Unit
V
V
V
V
mA
mA
mA
mA
pF
pF
100
20
150
4
Note 1: The TSPC932 outputs can drive series or parallel terminated 50
W
(or 50
W
to V
CC
/2) transmission lines on the incident edge
(see Applications Information section).
Note 2: Inputs have pull–up/pull–down resistors which affect current.
3.2. PLL INPUT REFERENCE CHARACTERISTICS
(TC = –55°C to 125°C, Vcc = 3.3V
5%)
Parameter
TCLK Input Rise/Fall Time
Reference Input Frequency
Reference Input Duty Cycle
Symbol
t
r,
t
f
f
ref
f
refDC
Note 3.
25
Comments
Min.
Max.
3.0
Note 3.
75
Unit
ns
MHz
Note 3: Minimum and Maximum input reference frequency is limited by the VCO lock range and feedback divider.
5/13
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