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IDT74FST163232PV8

产品描述Bus Exchanger, CBT/FST/QS/5C/B Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, SSOP-56
产品类别逻辑    逻辑   
文件大小119KB,共7页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

IDT74FST163232PV8概述

Bus Exchanger, CBT/FST/QS/5C/B Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74FST163232PV8规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码SSOP
包装说明SSOP, SSOP56,.4
针数56
Reach Compliance Codenot_compliant
系列CBT/FST/QS/5C/B
JESD-30 代码R-PDSO-G56
JESD-609代码e0
长度18.415 mm
逻辑集成电路类型BUS EXCHANGER
湿度敏感等级1
位数16
功能数量1
端口数量3
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码SSOP
封装等效代码SSOP56,.4
封装形状RECTANGULAR
封装形式SMALL OUTLINE, SHRINK PITCH
电源5 V
传播延迟(tpd)0.25 ns
认证状态Not Qualified
座面最大高度2.794 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式GULL WING
端子节距0.635 mm
端子位置DUAL
宽度7.493 mm

IDT74FST163232PV8文档预览

IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
INDUSTRIAL TEMPERATURE RANGE
16-BIT SYNCHRONOUS
2:1 MUX/DEMUX SWITCH
IDT74FST163232
FEATURES:
Bus switches provide zero delay paths
Extended commercial range of –40°C to +85°C
Low switch on-resistance
TTL-compatible input and output levels
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
Available in SSOP, TSSOP, and TVSOP Packages
Hot insertion capability
Very low power dissipation
DESCRIPTION:
The FST163232 belong to IDT's family of Bus switches. Bus switch
devices perform the function of connecting or isolating two ports without
providing any inherent current sink or source capability. Thus they
generate little or no noise of their own while providing a low resistance path
for an external driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this FET is
adequately forward-biased the device conducts and the resistance be-
tween input and output ports is small. Without adequate bias on the gate-
to-source junction of the FET, the FET is turned off, therefore with no V
CC
applied, the device has hot insertion capability.
The low on-resistance and simplicity of the connection between input and
output ports reduces the delay in this path to close to zero.
The FST163232 provides three 16-bit TTL- compatible ports that
support 2:1 multiplexing. The S
0,1
pins control mux select and switch
enable/disable. The S
0,1
inputs are synchronous and clocked on the rising
edge of CLK when
CLKEN
is low.
Port A can be connected to port B1 or port B2 or both ports B1 and B2.
FUNCTIONAL BLOCK DIAGRAM
CLKEN
CLK
S0
D
CE
CLK
S1
D
CE
CLK
1A
One of 16 Channels
1
B
1
1
B
2
INDUSTRIAL TEMPERATURE RANGE
1
c /-
1999
Integrated Device Technology, Inc.
OCTOBER 1999
DSC-5518/-
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1A
2
B
1
2
B
2
ABSOLUTE MAXIMUM RATINGS
(1)
56
55
54
53
52
51
50
49
48
47
46
45
44
Symbol
V
TERM(2)
1
B
1
1
B
2
Rating
Terminal Voltage with Respect to GND
Storage Temperature
Maximum Continuous Channel Current
Max.
–0.5 to +7
–65 to +150
128
Unit
V
°C
mA
FST LINK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SO56-1
SO56-2
SO56-3
T
STG
I
OUT
2A
3
B
1
3
B
2
3A
4
B
1
4
B
2
4A
5
B
1
5
B
2
5A
6
B
1
6
B
2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc, Control, and Switch terminals.
6A
7
B
1
CAPACITANCE
(1)
Symbol
Parameter
C
IN
Control Input Capacitance
C
I/O
C
I/O
Switch Input/Output
Capacitance, A Port
Switch Input/Output
Capacitance, B Port
Conditions
(2)
Switch Off
Switch Off
Typ.
6
17
12
Unit
pF
pF
pF
7A
8
B
1
8
B
2
7
B
2
8A
GND
V
CC
9
B
1
GND
Vcc
9A
10
B
1
10
B
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NOTES:
1. Capacitance is characterized but not tested.
2. T
A
= 25°C, f = 1MHz, V
IN
= 0V, V
OUT
= 0V
9
B
2
10A
11B
1
11B
2
12A
13
B
1
13
B
2
PIN DESCRIPTION
Pin Names
A
B
1
, B
2
S
0,1
CLK
CLKEN
I/O
I/O
I/O
I
I
I
Description
Bus A
Buses B
1,
B
2
Control Pins
Clock Input. Clocks S
0,1
on Rising Edge
Clock Enable Input
11A
12
B
1
12
B
2
13A
14
B
1
14
B
2
14A
15
B
1
15A
16
B
1
16
B
2
FUNCTION TABLE
S
1
X
L
L
H
H
S
0
X
L
H
L
H
CLK
X
(1)
CLKEN
H
L
L
L
L
Description
Last state
Disconnect
A to B
1
and A to B
2
A to B
1
or B
1
to A
A to B
2
or B
2
to A
15
B
2
16A
S
0
S
1
CLK
CLKEN
SSOP/ TSSOP/ TVSOP
TOP VIEW
NOTE:
1. H = HIGH Voltage level
L = LOW Voltage Level
X = Don’t Care
= Low-to-High Transition
2
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Conditions: T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OFF
I
CC
Parameter
Control Input HIGH Voltage
Control Input LOW Voltage
Control Input HIGH Current
Control Input LOW Current
Current during
Bus Switch DISCONNECT
Clamp Diode Voltage
Switch Power Off Leakage
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= 0V, V
IN
or V
O
5.5V
V
CC
= Max., V
IN
= GND or V
CC
V
CC
= Max., V
O
= 0 to 5V
Test Conditions
Guaranteed Logic HIGH for Control Inputs
Guaranteed Logic LOW for Control Inputs
V
CC
= Max.
V
I
= V
CC
V
I
= GND
Min.
2
Typ.
(1)
–0.7
0.1
Max.
0.8
±1
±1
±1
±1
–1.2
±1
3
V
µA
µA
FST LINK
Unit
V
V
µA
µA
BUS SWITCH IMPEDANCE OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Conditions: T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
R
ON
Parameter
Switch On Resistance
(2)
Test Conditions
Vcc = Min., V
IN
= 0V
I
ON
= 64mA
Vcc = Min., V
IN
= 0V
I
ON
= 30mA
Vcc = Min., V
IN
= 2.4V
I
ON
= 15mA
A(B) = 0V, B(A) = V
CC
Min.
100
Typ.
(1)
4
4
6
Max.
7
7
15
Unit
mA
I
OS
Short Circuit Current, A to B
(3)
NOTES:
1. Typical values are at Vcc = 5.0V, +25°C ambient.
2. The voltage drop between the indicated ports divided by the current through the switch.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
3
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4, 5)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Clock Pin Toggling
50% Duty Cycle
16 Switches Toggling
One Select Toggling at
50% of CLK frequency
V
CC
= Max.
Clock Pin Toggling
50% Duty Cycle
16 Switches Toggling
One Select Toggling at
50% of CLK frequency
V
CC
= Max.
Clock Pin Toggling
50% Duty Cycle
32 Switches Toggling
2 Select Pins Toggling at
50% of CLK frequency
V
CC
= Max.
f
CP
= 10MHz (CLK)
50% Duty Cycle
CLKEN
= LOW
S0 = HIGH or LOW
fi = 2.5MHz (S1)
16 Switches Toggling
V
CC
= Max.
f
CP
= 10MHz (CLK)
50% Duty Cycle
CLKEN
= LOW
S1 = HIGH
fi = 2.5MHz (S0)
16 Muxes Exchanging
V
CC
= Max.
f
CP
= 10MHz (CLK)
50% Duty Cycle
CLKEN
= LOW
S1 = LOW
fi = 2.5MHz (S0)
32 Switches Toggling
Min.
V
IN
= V
CC
V
IN
= GND
Typ.
(2)
0.5
Max.
1.5
Unit
mA
µ A/
MHz/
I
CCD
Dynamic Power Supply Current
(4, 5)
V
IN
= V
CC
V
IN
= GND
µ A/
MHz/
I
CCD
Dynamic Power Supply Current
(4, 5)
V
IN
= V
CC
V
IN
= GND
µ A/
MHz/
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
V
IN
= 3.4V
mA
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
V
IN
= 3.4V
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
V
IN
= 3.4V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. T
A
= –40°C to
+85°C
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND. Switch inputs do not contribute to
∆I
CC.
4. This parameter represents the current required to switch the internal capacitance of the control inputs at the specified frequency. Switch inputs generate
no significant power supply currents as they transition. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. C
PD
= I
CCD
/V
CC
C
PD
= Power Dissipation Capacitance
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
i
N)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
i
= Control Input Frequency
N = Number of Control Inputs Toggling at f
i
4
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Conditions: T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%
V
CC
= 5V ± 10%
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
BX
t
SU
t
H
t
SU
t
H
|Q
CI
|
|Q
DCI
|
Description
(1)
Data Propagation Delay
A to B, B to A
(2)
Switch CONNECT Delay
CLK↑ to A-B1 or A-B2
Switch CONNECT Delay
CLK↑ to B1-B2
Switch DISCONNECT Delay
CLK↑ to A, B
Switch EXCHANGE Delay
CLK↑ from A-B1 (B2) to A-B2 (B1)
Clock Enable Set-Up TIme
CLKEN
to CLK↑
Clock Enable Hold TIme
CLKEN
after CLK↑
Select Set-Up TIme
S
0
, S
1
to CLK↑
Select Hold TIme
S
0
, S
1
after CLK↑
Charge Injection During Switch DISCONNECT,
CLK↑ to A, B
(3)
Charge Injection During Switch DISCONNECT,
CLK↑ to A, B
(3)
Min.
1.5
1.5
1.9
1.8
1.9
1
1.9
1
Typ.
1.5
0.5
Max.
0.25
5.8
7.9
6.2
6.2
Min.
2.2
1.9
2.2
0.5
V
CC
= 4V
Max.
0.25
6.1
8.5
5.8
6.8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
pC
NOTES:
1. See test circuits and waveforms.
2. The bus switch contributes no Propagation Delay other than the RC Delay of the load interacting with the RC of the switch.
3. |Q
CI
| is the charge injection for a single switch DISCONNECT and applies to either single switches or multiplexers.
|Q
DCI
| is the charge injection for a multiplexer as the multiplexed port switches from one path to another. Charge injection is reduced because the
injection from the DISCONNECT of the first path is compensated by the CONNECT of the second path.
5

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