256Kx16 Bit High Speed Static RAM(3.3V Operating),
Operated at Commercial and Industrial Temperature Range.
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev.1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Release to Final Data Sheet
1. Delete Preliminary
2. Add 30pF capacitive in test load
3. Relex DC characteristics
Item
I
CC
10ns
12ns
15ns
I
SB
f=max.
I
SB1
f=0
I
DR
V
DR
=3.0V
Draft Data
Jan. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Rev. 2.0
Feb.11th.1998
Final
Previous
240mA
230mA
220mA
40mA
10 / 1mA
0.9mA
Current
250mA
245mA
240mA
50mA
10 / 1.2mA
1.0mA
Jun. 27th 1998
Final
Rev.2.1
Change operating current at Industrial Temperature range.
Previous spec.
Changed spec.
Items
(10/12/15ns part)
(10/12/15ns part)
I
CC
250/245/240mA
275/270/265mA
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.1
June 1998
PRELIMPreliminaryPPPPPPPPPINARY
KM616V4002B/BL, KM616V4002BI/BLI
256K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50mA(Max.)
(CMOS) : 10mA(Max.)
1.2mA(Max.)- L-Ver.
Operating KM616V4002B/BL - 10 : 250mA(Max.)
KM616V4002B/BL - 12 : 245mA(Max.)
KM616V4002B/BL - 15 : 240mA(Max.)
• Single 3.3
±0.3V
Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Low Data Retention Voltage : 2V(Min.) - L-Ver. Only
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O
1
~ I/O
8,
UB : I/O
9
~ I/O
16
• Standard Pin Configuration
KM616V4002BJ : 44-SOJ-400
KM616V4002BT : 44-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The KM616V4002B is a 4,194,304-bit high-speed Static Ran-
dom Access Memory organized as 262,144 words by 16 bits.
The KM616V4002B uses 16 common input and output lines
and has an output enable pin which operates faster than
address access time at read cycle. Also it allows that lower and
upper byte access by data byte control(UB, LB). The device is
fabricated using SAMSUNG′s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The KM616V4002B is packaged in a 400mil 44-pin plastic SOJ
or TSOP(II) forward.
PIN CONFIGURATION
(Top View)
A
0
A
1
A
2
A
3
A
4
1
2
3
4
5
6
7
8
9
44 A
17
43 A
16
42 A
15
41 OE
40 UB
39 LB
38 I/O
16
37 I/O
15
36 I/O
14
ORDERING INFORMATION
KM616V4002B/BL -10/12/15
KM616V4002BI/BLI -10/12/15
Commercial Temp.
Industrial Temp.
CS
I/O
1
I/O
2
I/O
3
I/O
4
10
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
~I/O
8
I/O
9
~I/O
16
Vcc 11
Vss 12
I/O
5
13
I/O
6
14
I/O
7
15
I/O
8
16
WE 17
SOJ/
TSOP2
35 I/O
13
34 Vss
33 Vcc
32 I/O
12
31 I/O
11
30 I/O
10
29 I/O
9
28 N.C
27 A
14
26 A
13
25 A
12
24 A
11
23 A
10
Pre-Charge Circuit
Row Select
Memory Array
512 Rows
512x16 Columns
A
5
18
A
6
19
A
7
20
A
8
21
A
9
22
Data
Cont.
Data
Cont.
Gen.
CLK
I/O Circuit &
Column Select
PIN FUNCTION
Pin Name
A
0
- A
17
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
1
~I/O
8
)
Upper-byte Control(I/O
9
~I/O
16
)
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
A
10
A
12
A
14
A
16
A
9
A
11
A
13
A
15
A
17
WE
CS
OE
WE
OE
UB
LB
CS
LB
UB
I/O
1
~ I/O
16
V
CC
V
SS
N.C
-2-
Rev 2.1
June 1998
PRELIMPreliminaryPPPPPPPPPINARY
KM616V4002B/BL, KM616V4002BI/BLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3**
0.8
Unit
V
V
V
V
NOTE: The above parameters are also guaranteed at industrial temperature range.
* V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA
** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Com
.
10ns
12ns
15ns
Ind.
10ns
12ns
15ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Normal
L-Ver.
Test Conditions
Min
-2
-2
-
-
-
-
-
-
-
-
-
-
2.4
Max
2
2
250
245
240
285
270
265
50
10
1.2
0.4
-
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
NOTE: The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* NOTE : Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
-3-
Rev 2.1
June 1998
PRELIMPreliminaryPPPPPPPPPINARY
KM616V4002B/BL, KM616V4002BI/BLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
NOTE: The above test conditions are also applied at industrial temperature range.
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
353Ω
319Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE
KM616V4002B/BL-10
KM616V4002B/BL-12
KM616V4002B/BL-15
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Symbol
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
OLZ
t
BLZ
t
HZ
t
OHZ
t
BHZ
t
OH
Min
10
-
-
-
-
3
0
0
0
0
0
3
Max
-
10
10
5
5
-
-
-
5
5
5
-
Min
12
-
-
-
-
3
0
0
0
0
0
3
Max
-
12
12
6
6
-
-
-
6
6
6
-
Min
15
-
-
-
-
3
0
0
0
0
0
3
Max
-
15
15
7
7
-
-
-
7
7
7
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
The above
parameters are also guaranteed at industrial temperature range.
-4-
Rev 2.1
June 1998
PRELIMPreliminaryPPPPPPPPPINARY
KM616V4002B/BL, KM616V4002BI/BLI
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB, LB Valid to End of Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
BW
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM616V4002B/BL-10
Min
10
7
0
7
7
10
7
0
0
5
0
3
Max
-
-
-
-
-
-
-
-
5
-
-
-
KM616V4002B/BL-12
Min
12
8
0
8
8
12
8
0
0
6
0
3
Max
-
-
-
-
-
-
-
-
6
-
-
-
KM616V4002B/BL-15
Min
15
10
0
10
10
15
10
0
0
7
0
3
Max
-
-
-
-
-
-
-
-
7
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS SRAM
NOTE: The above parameters are also guaranteed at industrial temperature range.
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