KMM377S6428AT3
Revision History
Revision 0.0 (June 7, 1999)
PC100 Registered DIMM
• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
• Symbol Change Notice
I
IL
I
IL
I
OL
Before
Input leakage current (inputs)
Input leakage current (I/O pins)
Output open @ DC characteristic table
I
LI
Io
After
Input leakage current
Output open @ DC characteristic table
•
Test Condition in
DC CHARACTERISTIC Change Notice
Symbol
I
CC2P ,
I
CC3P
I
CC2N ,
I
C C 3 N
I
C C 4
Before
CKE
≤
V
IL
(max), t
C C
= 15ns
C K E
≥
V
IH
(min), C S
≥
V
IH
(min), t
C C
= 15ns
Input signals are changed one time during 30ns
2 Banks activated
After
C K E
≤
V
IL
(max), t
C C
= 10ns
C K E
≥
V
IH
(min), CS
≥
V
IH
(min), t
C C
= 10ns
Input signals are changed one time during 20ns
4 Banks activated
Revision 0.1 (July 5, 1999)
• Added Notes @OPERATING AC PARAMETER
Notes : 5. For -H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
• Redefind feedback capacitor value to Cb, variable value @ Functional Block Diagram.
Revision 0.2 (April 29, 2000)
- Added the description of " Staktek’ stacking technology is Samsung’ stacking technology of choice."
s
s
Rev. 0.2 Apr. 2000
KMM377S6428AT3
PC100 Registered DIMM
KMM377S6428AT3 SDRAM DIMM (Intel 1.2 ver Base)
64Mx72 SDRAM DIMM with PLL & Register based on Stacked 64Mx4, 4Banks, 4K Ref., 3.3V SDRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM377S6428AT3 is a 64M bit x 72 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung KMM377S6428AT3 consists of eighteen CMOS Stacked
64Mx4 bit Synchronous DRAMs in two TSOP-II 400mil pack-
ages, three 18-bits Drive ICs for input control signal, one PLL
in 24-pin TSSOP package for clock and one 2K EEPROM in 8-
pin TSSOP package for Serial Presence Detect on a 168-pin
glass-epoxy substrate. Two 0.22uF and one 0.0022uF decou-
pling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The KMM377S6428AT3 is a Dual In-
line Memory Module and is intented for mounting into 168-pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
FEATURE
• Performance range
Part No.
KMM377S6428AT3-GH
KMM377S6428AT3-GL
•
•
•
•
•
Max Freq. (Speed)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4 , 8 page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,700mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
PIN NAMES
Pin
Back
Pin Name
Function
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
DD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
*CLK1
*A12
V
SS
CKE0
CS3
DQM6
DQM7
*A13
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
DD
V
DD
CLK0
V
SS
DU
CS2
DQM2
DQM3
DU
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ18
DQ19
V
DD
DQ20
NC
*V
R E F
*CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
*CLK2
NC
WP
**SDA
**SCL
V
DD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
141 DQ50
142 DQ51
143 V
DD
144 DQ52
NC
145
146 *V
REF
147 REGE
V
SS
148
149 DQ53
150 DQ54
151 DQ55
V
SS
152
153 DQ56
154 DQ57
155 DQ58
156 DQ59
157 V
DD
158 DQ60
159 DQ61
160 DQ62
161 DQ63
V
SS
162
163 *CLK3
NC
164
165 **SA0
166 **SA1
167 **SA2
168 V
DD
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0
CKE0
CS0 ~ CS3
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
*V
REF
REGE
SDA
SCL
SA0 ~ 2
DU
NC
WP
*
Address input (Multiplexed)
Select bank
Data input/output
Check bit (Data-in/data-out)
Clock input
Clock enable input
Chip select input
Row address strobe
Colume address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Register enable
Serial data I/O
Serial clock
Address in EEPROM
D o n
′
t use
No connection
Write protection
These pins are not used in this module.
**
T h e s e p i n s s h o u l d b e N C i n t h e s y s t e m
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 Apr. 2000
KMM377S6428AT3
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
PC100 Registered DIMM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9, CA11
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V
DD
through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP pin is connected to V
SS
through 47KΩ Resistor.
When WP is "high", EEPROM programming will be inhibited and the entire memory will
be write-protected.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
REGE
Register enable
DQ0 ~ 63
CB0 ~ 7
WP
V
DD
/V
SS
Data input/output
Check bit
Write protection
Power supply/ground
Rev. 0.2 Apr. 2000
KMM377S6428AT3
FUNCTIONAL BLOCK DIAGRAM
BCS1,B
2
CKE0
BCS0,B
0
CKE0
PCLK0
B
0
RAS,B
0
CAS,B
0
WE,B
0
BA0,B
0
BA1
B
0
A0~B
0
A11
BDQM0
DQ0~3
10Ω
PCLK1
CLK
CS1,CKE
D0L
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D1L
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D2L
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D3L
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D4L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D0U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D1U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D2U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D3U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D4U
CTL
Add
DQM
DQ0~3
PC100 Registered DIMM
BDQM4
DQ32~35
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D9L
CLK
CS1,CKE
D9U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D10U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D11U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D12U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D13U
CTL
Add
DQM
DQ0~3
DQ4~7
10Ω
PCLK2
DQ36~39
10Ω
CLK
CS0,CKE
D10L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D11L
CTL
Add
DQM
DQ0~3
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
10Ω
BDQM1
DQ8~11
10Ω
PCLK3
BDQM5
DQ40~43
D12L
DQ12~15
10Ω
PCLK4
DQ44~47
D13L
CB0~3
10Ω
BCS3,B
3
CKE0
BCS2,B
1
CKE0
PCLK5
CB4~7
BDQM2
DQ16~19
10Ω
PCLK6
CLK
CS1,CKE
D5L
CTL
Add
DQM
DQ0~3
CLK
CS1
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D5U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D6U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D7U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
D8U
CTL
Add
DQM
DQ0~3
BDQM6
DQ48~51
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
10Ω
D14L
CLK
CS1,CKE
D14U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D15U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D16U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D17U
CTL
Add
DQM
DQ0~3
D6L
D15L
DQ20~23
10Ω
PCLK7
DQ52~55
BDQM3
DQ24~27
10Ω
PCLK8
B
1
RAS,B
1
CAS,B
1
WE,B
1
BA0,B
1
BA1
B
1
A0~B
1
A11
DQ28~31
10Ω
CLK
CS1,CKE
D7L
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE
D8L
CTL
Add
DQM
DQ0~3
D16L
BDQM7
DQ56~59
D17L
DQ60~63
A
3
~A
10
,BA0
SN74ALVC162835
V
DD
B
0
A
3~
B
0
A
10,
B
0
BA0
B
1
A
3~
B
1
A
10,
B
1
BA0
V
SS
V
DD
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
PCLK
0PCL
K1
PCLK
2PCL
K3PC
LK4P
CLK5
PCLK
10kΩ
PCLK9
REGE
A
11
,BA1
SN74ALVC162835
CS2,CS3
CKE0
DQM2,3,6,7
LE
A
0
,A
1
,A
2
SN74ALVC162835
RAS,CAS,WE
CS0,CS1
DQM0,1,4,5
LE
OE
OE
B
0
A
0
,B
0
A
1
,B
0
A
2
B
1
A
0
,B
1
A
1
,B
1
A
2
B
0
RAS, B
0
CAS, B
0
WE
B
1
RAS, B
1
CAS, B
1
WE
BCS0,BCS1
BDQM0,1,4,5
LE
OE
B
0
A
11.
B
0
BA1
B
1
A
11.
B
1
BA1
BCS2,BCS3
B
0
CKE0,B
1
CKE0
B
2
CKE0,B
3
CKE0
BDQM2,3,6,7
CLK0
12pF
10Ω
CLK
Cb
*2
G
AGND
AVCC
CDC2510
FBOU
* Note
1. Unused clock termination : 10Ω and 12pF
2. The actual values of
Cb
will depend upon the PLL chosen.
Serial PD
SCL
WP
47KΩ
A0
A1
A2
SDA
SA0 SA1 SA2
Rev. 0.2 Apr. 2000
KMM377S6428AT3
PC100 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
*1
Control Signal(RAS,CAS,WE)
REG
*3
D
8
9
10
11
OUT
*1. Register Input
0
CLK
1
2
3
4
5
6
7
12
13
14
15
16
17
18
19
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
tSAC
tRAC(refer to *1)
1CLK
DQ
tRAC(refer to *2)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CAS latency(refer to *2)
=2CLK
tRDL
Row Active
Read
Command
Precharge
Command
Row Active
Write
Command
Precharge
Command
td, tr = Delay of register (74ALVC162835)
Notes :
1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVC162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D
IN
is to be issued 1clock after write command in external timing because D
IN
is issued directly to module.
: Don
′t
care
Rev. 0.2 Apr. 2000
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