16V8
PALCE16V8
Flash Erasable,
Reprogrammable CMOS PAL
®
Device
Features
• Active pull-up on data input pins
• Low power version (16V8L)
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 65 mA military (15 and 25 ns)
• Standard version has low power
— 90 mA max. commercial (10, 15, 25 ns)
— 115 mA max. commercial (7 ns)
— 130 mA max. military/industrial (10, 15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• PCI compliant
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• Up to 16 input terms and 8 outputs
•
7.5 ns com’l version
5 ns t
CO
5 ns t
S
7.5 ns t
PD
125-MHz state machine
•
10 ns military/industrial versions
7 ns t
CO
10 ns t
S
10 ns t
PD
62-MHz state machine
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE16V8 is a CMOS Flash Electrical Eras-
able second-generation programmable array logic device. It is
implemented with the familiar sum-of-product (AND-OR) logic
structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
GND
10
I
8
9
I
7
8
I
6
7
I
5
6
I
4
5
I
3
4
I
2
3
I
1
2
CLK/I
0
1
PROGRAMMABLE
AND ARRAY
(64 x 32)
8
8
8
8
8
8
8
8
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
11
OE/I
9
12
I/O
0
13
I/O
1
14
I/O
2
15
I/O
3
16
I/O
4
17
I/O
5
18
I/O
6
19
I/O
7
20
V
CC
16V8–1
Pin Configurations
CLK/I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
GND
I
8
GND
OE/I
9
I/O
0
I/O
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
OE/I
9
I
2
I
1
CLK/I
0
V
CC
I/O
7
I
3
I
4
I
5
I
6
I
7
16V8–2
DIP
Top View
PLCC/LCC
Top View
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10111213
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
16V8–3
Cypress Semiconductor Corporation
Document #: 38-03025 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 3, 1998
PALCE16V8
Selection Guide
t
PD
ns
Generic Part Number
PALCE16V8-5
PALCE16V8-7
PALCE16V8-10
PALCE16V8-15
PALCE16V8-25
PALCE16V8L-15
PALCE16V8L-25
Com’l/Ind
5
7.5
10
15
25
15
25
10
15
25
15
25
Mil
3
7
10
12
15
12
15
10
12
20
12
20
t
S
ns
Com’l/Ind
Mil
4
5
7
10
12
10
12
10
10
12
12
20
t
CO
ns
Com’l/Ind
Mil
115
115
90
90
90
55
55
130
130
130
65
65
I
CC
mA
Com’l
Mil/Ind
Shaded area contains preliminary information.
Functional Description
(continued)
The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,
a 300-mil cerdip, a 20-lead square ceramic leadless chip car-
rier, and a 20-lead square plastic leaded chip carrier.
The device provides up to 16 inputs and 8 outputs. The
PALCE16V8 can be electrically erased and reprogrammed.
The programmable macrocell enables the device to function
as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.
The PALCE16V8 features 8 product terms per output and 32
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE16V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE16V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE16V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE16V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Configuration Table
CG
0
0
0
1
1
1
CG
1
1
1
0
0
1
CL0
x
0
1
0
1
1
Cell Configuration
Registered Output
Combinatorial I/O
Combinatorial Output
Input
Combinatorial I/O
Devices Emulated
Registered Med PALs
Registered Med PALs
Small PALs
Small PALs
16L8 only
Document #: 38-03025 Rev. **
Page 2 of 13
PALCE16V8
Macrocell
To
Adjacent
Macrocell
1 1
0 X
1 0
OE
V
CC
1 1
1 0
0 0
0 1
CG
1
CL0
x
1 1
0 X
D
Q
Q
1 0
I/O
x
V
CC
CLK
CL1
x
1 0
1 1
0 X
CG
1
for pin 13 to 18
CG
0
for pin 12 and 19
CL0
x
From
Adjacent
Pin
16V8–4
Document #: 38-03025 Rev. **
Page 3 of 13
PALCE16V8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 24 mA
DC Programming Voltage............................................. 12.5V
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Military
[1]
Industrial
Ambient
Temperature
0
°
C to +75
°
C
–55
°
C to +125
°
C
–40
°
C to +85
°
C
V
CC
5V
±5%
5V
±10%
5V
±10%
Electrical Characteristics
Over the Operating Range
[2]
Parameter
V
OH
V
OL
V
IH
V
IL[4]
I
IH
I
IL[5]
I
SC
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input or I/O HIGH Leakage
Current
Input or I/O LOW Leakage
Current
Operating Power Supply
Current
V
CC
= Min.,
V
IN
= V
IH
or V
IL
V
CC
= Min.,
V
IN
= V
IH
or V
IL
Test Conditions
I
OH
= –3.2 mA
I
OH
= –2 mA
I
OL
= 24 mA
I
OL
= 12 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
2.0
–0.5
0.8
10
–100
–30
Com’l
–150
115
90
55
Mil/Ind
Mil.
Ind.
130
65
65
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
0.5
V
Min.
2.4
Max.
Unit
V
Guaranteed Input Logical HIGH Voltage for All Inputs
[3]
Guaranteed Input Logical LOW Voltage for All Inputs
[3]
3.5V < V
IN
< V
CC
0V < V
IN
< V
IN
(Max.)
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[6, 7]
V
CC
= Max.,
V
IL
= 0V, V
IH
= 3V,
Output Open,
f = 15 MHz
(counter)
5, 7 ns
10, 15, 25 ns
15L, 25L ns
10, 15, 25 ns
15L, 25L ns
15L, 25L ns
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2.0V @ f = 1 MHz
V
OUT
= 2.0V @ f = 1 MHz
Typ.
5
5
Unit
pF
pF
Endurance Characteristics
[7]
Parameter
N
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Min.
100
Max.
Unit
Cycles
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. V
IL
(Min.) is equal to –3.0V for pulse durations less than 20 ns.
5. The leakage current is due to the internal pull-up resistor on all pins.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03025 Rev. **
Page 4 of 13
PALCE16V8
AC Test Loads and Waveforms
ALL INPUT PULSES
3.0V
90%
GND
< 2 ns
10%
90%
10%
< 2 ns
16V8–5
5V
S1
R1
OUTPUT
R2
C
L
16V8–6
TEST POINT
Commercial
Specification
t
PD
, t
CO
t
PZX
, t
EA
t
PXZ
, t
ER
Closed
Z
·
H: Open
Z
·
L: Closed
H
·
Z: Open
L
·
Z: Closed
5 pF
S
1
C
L
50 pF
R
1
200Ω
R
2
390Ω
R
1
Military
R
2
750Ω
Measured Output Value
1.5V
1.5V
H
·
Z: V
OH
– 0.5V
L
·
Z: V
OL
+ 0.5V
390Ω
Document #: 38-03025 Rev. **
Page 5 of 13
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