Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
F
EATURES
•
Dual 2:1/1:2 MUX
•
Three LVDS outputs
•
Three differential inputs
•
Differential inputs can accept the following differential
levels: LVPECL, LVDS, CML
•
Loopback test mode available
•
Maximum output frequency: 2.5GHz
•
Part-to-part skew: 250ps (maximum)
•
Additive phase jitter, RMS: 0.05ps (typical)
•
Propagation delay: 550ps (maximum)
•
2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS85454-01 is a 2:1/1:2 Multiplexer and
a member of the HiPerClockS
TM
family of high
HiPerClockS™
performance clock solutions from ICS. The 2:1
Multiplexer allows one of 2 inputs to be select-
ed onto one output pin and the 1:2 MUX
switches one input to both of two outputs. This device
may be useful for multiplexing multi-rate Ethernet PHYs
which have 100Mbit and 1000Mbit transmit/receive
pairs onto an optical SFP module which has a single
transmit/receive pair. Another mode allows loop back
testing and allows the output of a PHY transmit pair to be
routed to the PHY input pair. For examples, please refer to
the Application Information section of the data sheet.
IC
S
The ICS85454-01 is optimized for applications requiring
very high performance and has a maximum operating
frequency in 2.5GHz. The device is packaged in a small,
3mm x 3mm VFQFN package, making it ideal for use on
space-constrained boards.
B
LOCK
D
IAGRAM
SELB
P
IN
A
SSIGNMENT
SELA
nQB
V
DD
QB
INA0
nINA0
QA0 1
nQA0 2
INB
nINB
16 15 14 13
12
11
10
9
5
INB
INA0
nINA0
INA1
nINA1
LOOP0
0
QA0
nQA0
QA1 3
nQA1 4
6
nINB
7
SELB
8
GND
0
QB
nQB
1
1
INA1
nINA1
ICS85454-01
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
LOOP1
QA1
nQA1
SELA
85454AK-01
www.icst.com/products/hiperclocks.html
1
REV. B OCTOBER 28, 2008
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
Pulldown
Select pin for QAx outputs. When HIGH, selects same inputs used for
Pulldown QB output. When LOW, selects INB input.
LVCMOS/LVTTL interface levels.
Power supply ground.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
Pulldown
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
Pulldown
Pulldown Non-inver ting differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
9
10
11
12
13
Name
QA0, nQA0
QA1, nQA1
IN B
nINB
SEL B
GND
nINA1
INA1
nINA0
INA0
V
DD
Output
Output
Input
In p u t
Input
Power
Input
Input
Input
Input
Power
Positive supply pin.
Select pin for QB outputs. When HIGH, selects INA1 input.
14
SELA
Input
Pulldown
When LOW, selects INA0 input. LVCMOS/LVTTL interface levels.
15, 16
nQB, QB
Output
Differential output pair. LVDS interface levels.
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
PULLUP
Parameter
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
37.5
37.5
Maximum
Units
kΩ
kΩ
T
ABLE
3. I
NPUT
C
ONTROL
F
UNCTION
T
ABLE
Control Inputs
SELA
0
1
0
1
SELB
0
0
1
1
Mode
LOOP0 selected
LOOP1 selected
Loopback mode: LOOP0
Loopback mode: LOOP1
85454AK-01
www.icst.com/products/hiperclocks.html
2
REV. B OCTOBER 28, 2008
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
51.5°C/W (0 lfpm)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
t o the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
90
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SELA, SELB
SELA, SELB
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
1.7
0
Typical
Maximum
V
DD
+ 0.3
0. 7
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%
Symbol
I
IH
Parameter
Input High Current
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Units
µA
µA
V
V
INAx, INB
150
150
150
nINAx, nINB
INAx, INB
I
IL
Input Low Current
-150
-150
-150
nINAx, nINB
V
PP
Peak-to-Peak Input Voltage
0.15
1.2
0.15
1.2
0.15
1.2
Commond Mode Input Voltage;
V
CMR
1.2
V
DD
1.2
V
DD
1.2
V
DD
NOTE 1, 2
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for INAx, nINAx and INB, nINB is V
DD
+ 0.3V.
85454AK-01
www.icst.com/products/hiperclocks.html
3
REV. B OCTOBER 28, 2008
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
-40°C
Min
250
0.93
Typ
350
1.18
Max
450
30
1.43
10
0.97
1.22
Min
250
25°C
Typ
350
Max
45 0
30
1.47
10
1.02
1.27
Min
250
85°C
Typ
350
Max
450
30
1.52
10
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%
Symbol
V
OD
∆
V
OD
V
OS
∆
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Units
mV
mV
V
mV
NOTE 1: Refer to Parameter Measurement Information, "2.5V Output Load Test Circuit" diagram.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.375V
TO
2.625V
Symbol
f
MAX
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
MUX Isolation
Output Rise/Fall Time
INAx to QB or INB to QAx
INAx to QAx
ƒ = 622.08MHz,
12kHz - 20MHz
@ 500MHz output
20% to 80%
50
250
300
250
0.05
55
250
Conditions
Minimum
Typical
Maximum
2.5
550
650
Units
GHz
ps
ps
ps
ps
dB
ps
t
PD
t
sk(pp)
t
jit
M U X
ISOLATION
t
R
/t
F
All parameters are measured
≤
1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85454AK-01
www.icst.com/products/hiperclocks.html
4
REV. B OCTOBER 28, 2008
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the
dBc Phase Noise.
This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
0
-10
-20
-30
-40
-50
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
Additive Phase Jitter
at
622.08MHz (12kHz - 20MHz)
= 0.05ps (typical)
SSB P
HASE
N
OISE
dBc/H
Z
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
85454AK-01
www.icst.com/products/hiperclocks.html
5
REV. B OCTOBER 28, 2008
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