HM5216326 Series
262,144-word
×
32-bit
×
2-bank Synchronous Graphic RAM
ADE-203-678 (Z)
Preliminary
Rev. 0.0
Nov. 20, 1996
Description
All inputs and outputs signals refers to the rising edge of the clock input. The HM5216326 provides 2
banks to realize better performance. 8 column block write function and write per bit function are provided
for graphic applications.
Features
•
3.3V Power supply
•
Clock frequency: 125 MHz/100 MHz/83 MHz (max)
•
LVTTL interface
•
•
•
•
2 Banks can operates simultaneously and independently
Burst read/write operation and burst read/ single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
Programmable
CAS
latency: 1/2/3
Byte control by DQM
8 column block write function with column address mask
Write per bit function (old mask)
Refresh cycles: 2048 refresh cycle/32 ms
2 variations of refresh
Auto refresh
Self refresh
•
•
•
•
•
•
Preliminary: This document contains information on a new product. Specifications and information
contained herein are subject to change without notice.
HM5216326 Series
Ordering Information
Type No.
HM5216326FP-8
HM5216326FP-10
HM5216326FP-12
Frequency
125 MHz
100 MHz
83 MHz
Package
100-pin plastic LQFP (FP-100H)
Pin Arrangement
HM5216326FP Series
DQ28
V
DD
Q
DQ27
DQ26
V
SS
Q
DQ25
DQ24
V
DD
Q
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
DD
Q
V
SS
V
DD
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
DD
Q
NC
DQM3
DQM1
CLK
CKE
DSF
NC
A9
DQ29
V
SS
Q
DQ30
DQ31
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
DQ0
DQ1
V
SS
Q
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
A3
A2
A1
A0
2
DQ3
V
DD
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
DD
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
DD
Q
V
DD
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
DD
Q
DQM0
DQM2
WE
CAS
RAS
CS
A10
A8
(Top view)
HM5216326 Series
Pin Description
Pin name
A0 to A10
Function
Address input
Row address
Column address
Bank select address (BS)
DQ0 to DQ31
CS
RAS
CAS
WE
DQM0 to DQM3
CLK
CKE
V
DD
V
SS
V
DD
Q
V
SS
Q
DSF
NC
Data-input/output
Chip select
Row address asserted bank enable
Column address asserted
Write enable
Byte input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ internal circuit
Ground for DQ internal circuit
Special function input flag
No connection
A0 to A9
A0 to A7
A10
3
HM5216326 Series
Block Diagram
A0 to A10
A0 to A7
A0 to A10
Column address
counter
Column address
buffer
Row address
buffer
Refresh
counter
Row decoder
Row decoder
Sense amplifier & I/O bus
Column decoder
Bank 0
1024 row
×
256 column
×
32 bit
Column decoder
Memory array
Sense amplifier & I/O bus
Memory array
Bank 1
1024 row
×
256 column
×
32 bit
DQ0 to DQ31
DQM3
DQM2
DQM1
DQM0
CKE
RAS
CAS
CLK
DSF
WE
CS
4
Color register
Mask register
Input
buffer
Output
buffer
Control logic &
timing generator
HM5216326 Series
Pin Functions
CLK (input pin):
CLK is the master clock input pin. The other input signals are referred at CLK rising
edge.
CS
(input pin):
When
CS
is Low, the command input cycle becomes valid. When
CS
is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS,
and
WE
(input pins):
These pins define operation commands (read, write, etc.) depending on
the combination of their voltage levels. For details, refer to the command operation section.
DSF (input pin):
DSF is a part of inputs of graphic commands of the HM5216326. If DSF is LOW, the
HM5216326 operates as standard synchronous DRAM.
A0 to A9 (input pins):
Row address (AX0 to AX9) is determined by A0 to A9 pins at the CLK rising
edge when a bank active command is input. Column address (AY0 to AY7) is determined by levels on A0
to A7 pins at the CLK rising edge when a read or write command is input. A9 determins precharge mode.
When A9 is low, only the bank selected by A10 (BS) is precharged by a precharge command. When A9 is
high, both banks are precharged by a precharge command.
A10 (input pin):
A10 is the bank select signal (BS). The memory array of the HM5216326 is divided into
the bank 0 and the bank 1, both contain 1024 row
×
256 column
×
32 bits. If A10 is Low, the bank 0 is
selected, and if A10 is High, the bank 1 is selected.
CKE (input pin):
By referring low level on CKE pin, HM5216326 determines to go into clock suspend
modes or power down modes. When refresh command is input, low level on this pin is also referred to turn
on self refresh process.
DQM0, DQM1, DQM2 and DQM3 (input pins):
DQM0 applies to DQ0 to DQ7. DQM1 applies to DQ8
to DQ15. DQM2 applies to DQ16 to DQ23. DQM3 applies to DQ24 to DQ31. In read mode, referring
high level on DQM pins, HM5216326 floats related DQ pins. In write mode, referring high level on DQM
pins, HM5216326 ignores input data through related DQ pins.
DQ0 to DQ31 (input/output):
These are the data line for the HM5216326.
V
DD
and V
DD
Q (power supply pins):
3.3 V is applied. (V
DD
is for the internal circuit and V
DD
Q is power
supply pin for DQ output buffer.)
V
SS
and V
SS
Q (power supply pins):
Ground is connected. (V
SS
is for the internal circuit and V
SS
Q is for
DQ output buffer.)
5
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