HM62W8128D Series
1 M SRAM (128-kword
×
8-bit)
ADE-203-998 (Z)
Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM62W8128D Series is 1-Mbit static RAM organized 131,072-kword
×
8-bit.
HM62W8128D Series has realized higher density, higher performance and low power consumption by
employing Hi-CMOS process technology. The HM62W8128D Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It has package variations of standard 32-
pin plastic SOP and standard 32-pin plastic TSOPI.
Features
•
Single 3.3 V supply: 3.3 V
±
0.3 V
•
Access time: 55 ns/70 ns (max)
•
Power dissipation
Active: 19.8 mW/MHz (typ)
Standby: 3.3
µW
(typ)
•
Completely static memory.
No clock or timing strobe required
•
Equal access and cycle times
•
Common data input and output
Three state output
•
Directly LV-TTL compatible all inputs
•
Battery backup operation
2 chip selection for battery backup
HM62W8128D Series
Ordering Information
Type No.
HM62W8128DLFP-5
HM62W8128DLFP-7
Access time
55 ns
70 ns
Package
525-mil 32-pin plastic SOP (FP-32D)
HM62W8128DLFP-5SL 55 ns
HM62W8128DLFP-7SL 70 ns
HM62W8128DLFP-5UL 55 ns
HM62W8128DLFP-7UL 70 ns
HM62W8128DLTS-5
HM62W8128DLTS-7
55 ns
70 ns
8
×
13.4 mm 32-pin plastic TSOP I (TFP-32DC)
HM62W8128DLTS-5SL 55 ns
HM62W8128DLTS-7SL 70 ns
HM62W8128DLTS-5UL 55 ns
HM62W8128DLTS-7UL 70 ns
HM62W8128DLT-5
HM62W8128DLT-7
HM62W8128DLT-5SL
HM62W8128DLT-7SL
HM62W8128DLT-5UL
HM62W8128DLT-7UL
HM62W8128DLR-5
HM62W8128DLR-7
HM62W8128DLR-5SL
HM62W8128DLR-7SL
HM62W8128DLR-5UL
HM62W8128DLR-7UL
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
Reverse-bend type 8
×
20 mm 32-pin plastic TSOP I (TFP-32DR)
Normal-bend type 8
×
20 mm 32-pin plastic TSOP I (TFP-32D)
2
HM62W8128D Series
Operation Table
CS1
H
L
L
L
L
L
L
CS2
H
L
L
H
H
H
H
WE
×
×
×
H
L
L
H
OE
×
×
×
L
H
L
H
I/O
High-Z
High-Z
High-Z
Dout
Din
Din
High-Z
Operation
Standby
Standby
Standby
Read
Write
Write
Output disable
Note: H: V
IH
, L: V
IL
,
×:
V
IH
or V
IL
Absolute Maximum Ratings
Parameter
Power supply voltage relative to V
SS
Terminal voltage on any pin relative to V
SS
Power dissipation
Storage temperature range
Storage temperature range under bias
Symbol
V
CC
V
T
P
T
Tstg
Tbias
Value
–0.5 to +4.6
–0.5*
1
to V
CC
+ 0.3*
2
1.0
–55 to +125
–20 to +85
Unit
V
V
W
°C
°C
Notes: 1. V
T
min: –1.5 V for pulse half-width
≤
30 ns
2. Maximum voltage is +4.6 V
DC Operating Conditions
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high voltage
Input low voltage
Ambient temperature range
Note:
V
IH
V
IL
Ta
Min
3.0
0
2.4
–0.3
–20
Typ
3.3
0
—
—
—
Max
3.6
0
V
CC
+ 0.3
0.4
+70
Unit
V
V
V
V
°C
1
Note
1. V
IL
min: –1.5 V for pulse half-width
≤
30 ns
5
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