HM621100A Series
1048576-word
×
1-bit High Speed CMOS Static RAM
The Hitachi HM621100A is a high speed 1M
Static RAM organized as 1048576-word
×
1-bit. It
realizes high speed access time (20/25/35 ns) and
low power consumption, employing CMOS
process technology and high speed circuit
designing technology. It is most advantageous for
the field where high speed and high density
memory is required, such as the cache memory for
main frame or 32-bit MPU.
The HM621100A, packaged in a 400-mil plastic
SOJ is available for high density mounting.
Ordering Information
Type No.
Access time Package
——————————————————————–
HM621100AP-20
20 ns
400-mil
————————————————–
28-pin
HM621100AP-25
25 ns
plastic DIP
————————————————–
(DP-28C)
HM621100AP-35
35 ns
————————————————–
HM621100ALP-20
20 ns
————————————————–
HM621100ALP-25
25 ns
————————————————–
HM621100ALP-35
35 ns
——————————————————————–
HM621100AJP-20
20 ns
400-mil
————————————————–
28-pin
HM621100AJP-25
25 ns
plastic SOJ
————————————————–
(CP-28D)
HM621100AJP-35
35 ns
————————————————–
HM621100ALJP-20 20 ns
————————————————–
HM621100ALJP-25 25 ns
————————————————–
HM621100ALJP-35 35 ns
——————————————————————–
Features
• Single 5 V supply and high density 28-pin
package (DIP and SOJ)
• High speed
Access time: 20/25/35 ns (max)
• Low power dissipation
Active mode: 350 mW (typ)
Standby mode: 100 µW (typ)
• Completely static memory required
No clock or timing strobe required
• Equal access and cycle time
• Directly TTL compatible
All inputs and outputs
1
HM621100A Series
Pin Arrangement
A0
A1
A2
A3
A4
A5
NC
A6
A7
A8
A9
Q
WE
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(Top view)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A19
A18
A17
A16
A15
A14
NC
A13
A12
A11
A10
D
CS
HM621100A Series
Pin Description
Pin Name
Function
——————————————————————–
A0 – A19
Address
——————————————————————–
D
Input
——————————————————————–
Q
Output
——————————————————————–
CS
Chip select
——————————————————————–
WE
Write enable
——————————————————————–
V
CC
Power supply
——————————————————————–
V
SS
Ground
——————————————————————–
Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
A9
Din
V
CC
Row
decoder
Memory array
512
×
2048
V
SS
Column I/O
Dout
Column decoder
CS
WE
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A0
2
HM621100A Series
Function Table
HM621100A Series
CS
WE
Mode
V
CC
current
Output pin
Ref. cycle
———————————————————————————————————————————————–
H
X
Not selected
I
SB
, I
SB1
High-Z
—
———————————————————————————————————————————————–
L
H
Read
I
CC
Dout
Read cycle
———————————————————————————————————————————————–
L
L
Write
I
CC
High-Z
Write cycle
———————————————————————————————————————————————–
Note: X : H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
———————————————————————————————————————————————–
Voltage on any pin relative to V
SS
Vin
–0.5
*1
to +7.0
V
———————————————————————————————————————————————–
Power dissipation
P
T
1.0
W
———————————————————————————————————————————————–
Operating temperature range
Topr
0 to +70
°C
———————————————————————————————————————————————–
Storage temperature range
Tstg
–55 to +125
°C
———————————————————————————————————————————————–
Storage temperature range under bias
Tbias
–10 to +85
°C
———————————————————————————————————————————————–
Note: 1. Vin min = –2.0 V for pulse width
≤
10 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
———————————————————————————————————————————————–
Supply voltage
V
CC
4.5
5.0
5.5
V
———————————————————————————————–
V
SS
0
0
0
V
———————————————————————————————————————————————–
Input high (logic 1) voltage
V
IH
2.2
—
6.0
V
———————————————————————————————————————————————–
Input low (logic 0) voltage
V
IL
–0.5
*1
—
0.8
V
———————————————————————————————————————————————–
Note: 1. V
IL
min = –2.0 V for pulse width
≤
10 ns.
3
HM621100A Series
HM621100A Series
DC Characteristics
(Ta = 0 to +70°C, V
CC
= 5 V ± 10%, V
SS
= 0 V)
HM621100A-20
HM621100A-25/35
————————– —————————
Parameter
Symbol Min Typ
*1
Max Min Typ
*1
Max Unit Test conditions
———————————————————————————————————————————————–
Input leakage
|I
LI
|
—
—
2.0
—
—
2.0
µA
V
CC
= max
current
Vin = V
SS
to V
CC
———————————————————————————————————————————————–
Output leakage
|I
LO
|
—
—
2.0
—
—
2.0
µA
CS
= V
IH
current
V
I/O
= V
SS
to V
CC
———————————————————————————————————————————————–
Operating power
I
CC
—
—
150 —
—
120 mA
CS
= V
IL
, I
I/O
= 0 mA,
supply current
min cycle
———————————————————————————————————————————————–
Standby power
I
SB
—
—
60
—
—
40
mA
CS
= V
IH
, min cycle
supply current
———————————————————————————————————————————————–
Standby power
I
SB1*2
—
0.02 2.0
—
0.02 2.0
mA
CS
≥
V
CC
–0.2 V
supply current (1)
——————————————————————————
0 V
≤
Vin
≤
0.2 V or
I
SB1*3
—
—
100 —
—
100 µA
Vin
≥
V
CC
–0.2 V
———————————————————————————————————————————————–
Output low voltage
V
OL
—
—
0.4
—
—
0.4
V
I
OL
= 8 mA
———————————————————————————————————————————————–
Output high voltage
V
OH
2.4
—
—
2.4
—
—
V
I
OH
= –4 mA
———————————————————————————————————————————————–
Notes: 1. Typical values are at V
CC
= 5.0 V, Ta = +25°C and not guaranteed.
2. P and JP version
3. LP and LJP version
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Min
Max
Unit
Test conditions
———————————————————————————————————————————————–
Input capacitance
Cin
—
5
*2
pF
Vin = 0 V
—————
6
*3
———————————————————————————————————————————————–
Output capacitance
Cout
—
8
pF
Vout = 0 V
———————————————————————————————————————————————–
Note: 1. This parameter is sampled and not 100% tested.
2. SOJ package
3. DIP package
4
HM621100A Series
Test Conditions
• Input pulse levels: 0 V to 3.0 V
• Input rise and fall times: 4 ns
• Input timing reference levels: 1.5 V
HM621100A Series
AC Characteristics
(Ta = 0 to +70°C, V
CC
= 5 V ± 10%, unless otherwise noted.)
• Output timing reference levels: 1.5 V
• Output load: See figures
+5V
480
Ω
Dout
255
Ω
30 pF
*1
Dout
255
Ω
+5V
480
Ω
5 pF
*1
Output load (A)
Note: 1. Including scope and jig
Output load (B)
(For t
HZ
, t
LZ
, t
WZ
and t
OW
)
Read Cycle
HM621100A-20
HM621100A-25
HM621100A-35
——————
——————
——————
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
———————————————————————————————————————————————–
Read cycle time
t
RC
20
—
25
—
35
—
ns
———————————————————————————————————————————————–
Address access time
t
AA
—
20
—
25
—
35
ns
———————————————————————————————————————————————–
Chip select access time
t
ACS
—
20
—
25
—
35
ns
———————————————————————————————————————————————–
Chip selection to output in low-Z
t
LZ*1
5
—
5
—
5
—
ns
———————————————————————————————————————————————–
Chip deselection to output in high-Z
t
HZ*1
0
10
0
12
0
15
ns
———————————————————————————————————————————————–
Output hold from address change
t
OH
5
—
5
—
5
—
ns
———————————————————————————————————————————————–
Chip selection to power up time
t
PU
0
—
0
—
0
—
ns
———————————————————————————————————————————————–
Chip deselection to power down time t
PD
—
12
—
15
—
25
ns
———————————————————————————————————————————————–
5
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