Supertex inc.
250V Low Charge Injection,
8-Channel, High Voltage Analog Switch
Features
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HVCMOS
®
technology for high performance
Very low quiescent power dissipation (-10µA)
Low parasitic capacitances
DC to 50MHz small signal frequency response
-60dB typical output off isolation at 5.0MHz
CMOS logic circuitry for low power
Excellent noise immunity
On-chip shift register, latch and clear logic circuitry
Flexible high voltage supplies
Surface mount packages
HV214
General Description
The Supertex HV214 is a low charge injection, 8-channel, high
voltage, analog switch integrated circuit (IC) intended for use in
applications requiring high voltage switching controlled by low
voltage control signals, such as medical ultrasound imaging,
piezoelectric transducer drivers, inkjet printer heads and optical
MEMS modules.
Input data is shifted into an 8-bit shift register that can then be
retained in an 8-bit latch. To reduce any possible clock feedthrough
noise, the latch enable bar should be left high until all bits are
clocked in. Data are clocked in during the rising edge of the clock.
Using HVCMOS
®
technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efficient control of high voltage analog signals.
The device is suitable for various combinations of high voltage
supplies, e.g., V
PP
/V
NN
: +40V/-210V, +125V/-125V, +210V/-40V.
Applications
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Medical ultrasound imaging
Non-destructive evaluation
Inkjet printer heads
Optical MEMS modules
Block Diagram
Level Output
Latches Shifters Switches
D
LE
CL
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
VNN VPP
D
LE
CL
D
LE
CL
DIN
8-Bit
Shift
Register
CLK
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
DOUT
VDD
Doc.# DSFP-HV214
C070713
LE CL
Supertex inc.
www.supertex.com
HV214
Ordering Information
Part Number
HV214FG-G
HV214FG-G M931
HV214PJ-G
HV214PJ-G M904
Package Option
48-Lead LQFP
28-Lead PLCC
Packing
250/Tray
1000/Reel
38/Tube
500/Reel
48-Lead LQFP
(top view)
1 28
4
26
Pin Configuration
1
48
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
V
DD
logic power supply voltage
V
PP
- V
NN
supply voltage
V
PP
positive high voltage supply
V
NN
negative high voltage supply
Logic input voltages
Analog signal range
Peak analog signal current/channel
Storage temperature
Power dissipation:
48-Lead LQFP
28-Lead PLCC
O
Value
-0.5V to +15V
260V
-0.5V to V
NN
+250V
+0.5V to -260V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
2.5A
-65 C to +150 C
O
28-Lead PLCC
(top view)
Product Marking
Top Marking
YYWW
HV214FG
1.0W
1.2W
LLLLLLLLL
Bottom Marking
CCCCCCCC
AAA
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
Operating Conditions
Sym
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Parameter
Logic power supply voltage
Positive high voltage supply
Negative high voltage supply
High level input logic voltage
Low-level input logic voltage
Analog signal voltage
peak-to-peak
Operating free air temperature
Value
4.5V to 13.2V
40V to V
NN
+250V
-40V to -210V
V
DD
-1.5V to V
DD
0V to 1.5V
V
NN
+10V to V
PP
-10V
0
O
C to 70
O
C
Top Marking
HV214PJ
YYWW
LLLLLLLLLL
48-Lead LQFP
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Bottom Marking
CCCCCCCCCCC
AAA
Package may or may not include the following marks: Si or
28-Lead PLCC
Typical Thermal Resistance
Package
48-Lead LQFP
28-Lead PLCC
θ
ja
52
O
C/W
48
O
C/W
Doc.# DSFP-HV214
C070713
2
Supertex inc.
www.supertex.com
HV214
DC Electrical Characteristics
(T
Sym
Parameter
A
= 25
O
C, over recommended operating conditions unless otherwise noted)
Min
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
23
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
55
49
42
36
38
32
20
-
10
300
500
50
-50
50
-50
2.0
50
7.0
5.0
5.0
-7.0
-5.0
-5.0
10
4.0
-
-
10
70
Units Conditions
I
SIG
= 5.0mA
I
SIG
= 5.0mA
I
SIG
= 5.0mA
V
PP
= +40V
I
SIG
= 200mA V
NN
= -210V
V
PP
= +125V
I
SIG
= 200mA V
NN
= -125V
V
PP
= +210V
I
SIG
= 200mA V
NN
= -40V
R
ONS
Small signal switch on-resistance
Ω
ΔR
ONS
R
ONL
I
SOL
V
OS
I
PPQ
I
NNQ
I
PPQ
I
NNQ
I
SW
f
SW
Small signal switch
on-resistance matching
Large signal switch on-resistance
Switch off leakage per switch
DC offset switch off
DC offset switch on
Quiescent V
PP
supply current
Quiescent V
NN
supply current
Quiescent V
PP
supply current
Quiescent V
NN
supply current
Switch output peak current
Output switch frequency
-
-
-
-
-
-
-
-
-
-
-
-
%
Ω
µA
mV
mV
µA
µA
µA
µA
A
kHz
I
SIG
= 5.0mA, V
PP
= +125V, V
NN
= -125V
V
SIG
= V
PP
-10V, I
SIG
= 1.0A
V
SIG
= V
PP
-10V & V
NN
+10V
R
LOAD
= 100kΩ
R
LOAD
= 100kΩ
All switches off
All switches off
All switches on, I
SW
= 5.0mA
All switches on, I
SW
= 5.0mA
V
SIG
duty cycle 0.1%
Duty cycle = 50%
V
PP
= +40V
V
NN
= -210V
All output switches are
turning on and off at
50kHz with no load
I
PP
Average V
PP
supply current
-
-
-
mA
V
PP
= +210V
V
NN
= -40V
V
PP
= +40V
V
NN
= -210V
V
PP
= +125V
V
NN
= -125V
I
NN
Average V
NN
supply current
-
-
mA
V
PP
= +210V
V
NN
= -40V
mA
µA
mA
mA
pF
O
V
PP
= +125V
V
NN
= -125V
All output switches are
turning on and off at
50kHz with no load
I
DD
I
DDQ
I
SOR
I
SINK
C
IN
T
A
Average V
DD
supply current
Quiescent V
DD
supply current
Data out source current
Data out sink current
Large input capacitance
Ambient temperature range
-
-
45
45
-
0
f
CLK
= 5.0MHz, V
DD
= 5.0V
---
V
OUT
= V
DD
-0.7V
V
OUT
= 0.7V
---
---
C
Doc.# DSFP-HV214
C070713
3
Supertex inc.
www.supertex.com
HV214
AC Electrical Characteristics
(V
Sym
t
SD
t
WLE
t
DO
t
WCL
t
SU
t
H
f
CLK
t
R
, t
F
T
ON
T
OFF
dv/dt
Parameter
Set-up time before LE rises
Time width of LE
Clock delay time to data out
Time width of CL
Set-up time data to clock
Hold time data from clock
Clock frequency
Clock rise and fall times
Turn-on time
Turn-off time
Maximum V
SIG
slew rate
DD
= 5.0V, T
A
= 25
O
C, over recommended operating conditions unless otherwise noted)
Min
150
150
-
150
15
35
-
-
-
-
-
-
-
-30
-58
-60
-
5.0
25
-
-
-
-
-
-
Typ
-
-
-
-
8.0
-
-
-
-
-
-
-
-
-
-
-
-
12
38
-
-
-
-
-
-
Max
-
-
150
-
-
-
5.0
50
5.0
5.0
20
20
20
-
-
-
300
17
50
200
200
200
200
200
200
Units Conditions
ns
ns
ns
ns
ns
ns
MHz
ns
µs
µs
V/ns
---
---
---
---
---
---
50% duty cycle, f
DATA
= f
CLK
/2
---
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
PP
= +40V, V
NN
= -160V
V
PP
= +125V, V
NN
= -100V
V
PP
= +210V, V
NN
= -40V
dB
dB
mA
pF
pF
f = 5.0MHz, 1kΩ//15pF load
f = 5.0MHz, 50Ω load
f = 5.0MHz, 50Ω load
300ns pulse width, 2% duty cycle
0V, f = 1.0MHz
0V, f = 1.0MHz
V
PP
= +40V, V
NN
= -210V, R
LOAD
= 50Ω
mV
V
PP
= +125V, V
NN
= -125V, R
LOAD
= 50Ω
V
PP
= +210V, V
NN
= -40V, R
LOAD
= 50Ω
K
O
K
CR
I
ID
C
SG(OFF)
C
SG(ON)
+V
SPK
-V
SPK
+V
SPK
-V
SPK
+V
SPK
-V
SPK
Off isolation
Switch crosstalk
Output switch isolation diode current
Off capacitance SW to GND
On capacitance SW to GND
Output voltage spike
Power Up/Down Sequence:
1.
Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2. V
SIG
must be V
NN
≤ V
SIG
≤ V
PP
or floating during power up/down transistion.
3. Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less than 1.0msec.
Doc.# DSFP-HV214
C070713
4
Supertex inc.
www.supertex.com
HV214
Truth Table
Data in 8-Bit Shift Register
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
OFF
Hold Previous State
OFF
OFF
OFF
OFF
OFF
OFF
Output Switch State
SW0
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L→H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the
latch.
4. D
OUT
is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
Logic Timing Waveforms
D
N+1
D
N
50%
50%
D
N-1
DATA
IN
LE
50%
50%
t
WLE
t
SD
CLOCK
t
SU
50%
t
h
50%
t
DO
DATA
OUT
V
OUT
(typ)
OFF
ON
CLR
50%
t
WCL
50%
50%
t
OFF
90%
10%
t
ON
Doc.# DSFP-HV214
C070713
5
Supertex inc.
www.supertex.com
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