Data Sheet
November 2006
USS2000 Four-Port
USB2.0 PCI-to-USB Host Controller
1 Features
32-bit, 33 MHz PCI interface compliant with
PCI
Local Bus Specification
Revision 2.2.
Four downstream USB ports.
Compliant with
Universal Serial Bus Specification
Revision 2.0.
Embedded OHCI core compliant with
OpenHCI
Open Host Controller Interface Specification for
USB
Release 1.0a.
Embedded EHCI core compliant with
Enhanced
Host Controller Interface Specification
Revision
1.0.
Compatible with
Microsoft Windows
®
standard
OpenHCI and EHCI drivers.
Listed on
Windows
hardware compatibility list
http://testedproducts.windowsmarketplace.com/.
Supported on
Mac OS
®
10.3 and higher and on
Linux
®
2.4.22 and higher.
3 V or 5 V switchable PCI signaling.
Low-power mode and wake-up compatible with
PCI Power Management Interface Specification
Revision 1.1.
Integrated high-speed, full-speed, and low-speed
USB transceivers.
Integrated PLL creates all required EHCI and
OHCI clocks from 30 MHz clock input.
Support for legacy keyboard and mouse.
Available in two package types:
— 128 TQFP.
— 161 FSBGA*.
Evaluation kit:
— PCI card.
— Schematics.
— Gerber files.
— Data sheets.
0.2
µm
technology.
Provides five USB host controllers:
— Four OHCI (12 Mbits/s each).
— One EHCI (480 Mbits/s).
* The term pin is used throughout the text, but if an FSBGA pack-
age is used, then the term ball is assumed to replace the term
pin.
2 Applications
Seamless integration with 3 V or 5 V PCI-based
computer products.
Supports high-speed, full-speed, or low-speed
USB-compliant devices and hubs connected to
any port.
Simultaneous operation of multiple high-perfor-
mance devices.
3 Description
The Agere USS2000 provides a single-chip, four-port
PCI-to-universal serial bus (USB) 2.0 solution. The
USS2000 interfaces directly to a 32-bit, 33 MHz PCI
bus and is ideal for either onboard applications or
add-in card applications. It can easily be configured
to communicate in either a 3 V PCI environment or
5 V PCI environment simply by selecting the appro-
priate communications voltage level on the VIO input
pin.
The USS2000 provides four downstream USB ports
for connectivity with a USB2.0 compliant device or
hub. High-speed (480 Mbits/s), full-speed
(12 Mbits/s), or low-speed (1.5 Mbits/s) peripherals
are supported along with all of the USB transfer
types: control, interrupt, bulk, or isochronous. Split
transaction support is also provided for communica-
tion with USB2.0 high-speed hubs. The USS2000’s
OpenHCI compliance offers USB performance bene-
fits and reduced CPU overhead compared to many
other USB host controllers. EHCI compliance
provides connectivity of high-speed USB2.0 devices
to operate up to 480 Mbits/s.
USS2000 Four-Port
USB2.0 PCI-to-USB Host Controller
Data Sheet
November 2006
Table of Contents
Contents
Page
1 Features ............................................................................................................................................................... 1
2 Applications .......................................................................................................................................................... 1
3 Description ............................................................................................................................................................ 1
4 Pin Information ..................................................................................................................................................... 8
5 Ball Information ................................................................................................................................................... 10
6 Pin/Ball Information ............................................................................................................................................ 13
7 System Configuration ......................................................................................................................................... 16
8 PCI Register Overview ....................................................................................................................................... 17
9 PCI Configuration Registers—Detailed Definition .............................................................................................. 19
9.1 Wake-Up Enable Register (40h) (Only OHCI Uses This Register) ...........................................................23
9.2 Special-Subsystem Write Capability Register (4Ch) .................................................................................23
9.3 Capabilities Identifier (Cap_ID) Register (50h) .........................................................................................24
9.4 Next Item Pointer Register (51h) ..............................................................................................................24
9.5 Power Management Capabilities Register (52h—53h) .............................................................................25
9.6 Power Management Control/Status Register (54h—55h) ........................................................................25
9.7 Power Management Control/Status Bridge (56h) .....................................................................................26
9.8 Power Management Data Register (57h) .................................................................................................26
9.9 Power Consumption/Dissipation Reporting ..............................................................................................26
9.10 Serial Bus Release Number (60h) (Only EHCI Uses This Register) ......................................................26
9.11 Frame Length Adjust Register (61h) (Only EHCI Uses This Register) ...................................................27
9.12 Port Wake Capability (62h) (Only EHCI Uses This Register) .................................................................27
9.13 Microframe Cache (6Ch) (Only EHCI Uses This Register) Vendor Specific ...........................................27
10 OHCI Registers ................................................................................................................................................ 28
11 Legacy Support Registers ................................................................................................................................ 35
11.1 HceInput Register ...................................................................................................................................35
11.2 HceOutput Register ................................................................................................................................36
11.3 HceStatus Register .................................................................................................................................36
11.4 HceControl Register ...............................................................................................................................37
12 EHCI Capability Registers ................................................................................................................................ 38
12.1 CAPLENGTH—Capability Registers Length ..........................................................................................38
12.2 HCIVERSION—Host Controller Interface Version Number ....................................................................38
12.3 HCSPARAMS—Structural Parameters ...................................................................................................38
12.4 HCCPARAMS Capability Parameters .....................................................................................................40
13 EHCI Operational Registers ............................................................................................................................. 41
13.1 USBCMD—USB Command Register .....................................................................................................41
13.2 USBSTS—USB Status Register .............................................................................................................44
13.3 USBINTR—USB Interrupt Enable Register ............................................................................................45
13.4 FRINDEX—Frame Index Register ..........................................................................................................46
13.5 CTRLDSSEGMENT—Control Data Structure Segment Register ..........................................................47
13.6 PERIODICLISTBASE—Periodic Frame List Base Address Register .....................................................48
13.7 ASYNCLISTADDR—Current Asynchronous List Address Register .......................................................48
13.8 CONFIGFLAG—Configure Flag Register ...............................................................................................49
13.9 PORTSC—Port Status and Control Registers ........................................................................................49
14 Connection Instructions .................................................................................................................................... 54
14.1 PCI Connection Instructions ...................................................................................................................54
14.2 USB Connection Instructions ..................................................................................................................54
14.3 Test Mode Connections ..........................................................................................................................55
15 Power Connection Recommendations ............................................................................................................. 56
16 Crystal Selection Considerations ...................................................................................................................... 57
16.1 Load Capacitance ...................................................................................................................................57
16.2 Adjustment to Crystal Loading ................................................................................................................57
16.3 Crystal/Board Layout ..............................................................................................................................57
2
Agere Systems Inc.
Data Sheet
November 2006
USS2000 Four-Port
USB2.0 PCI-to-USB Host Controller
Table of Contents
(continued)
Contents
Page
17 Power Management Interface .......................................................................................................................... 58
18 NAND Tree Mode ............................................................................................................................................. 59
19 Absolute Maximum Ratings .............................................................................................................................. 60
20 Electrical Characteristics .................................................................................................................................. 61
20.1 PCI Electrical Characteristics .................................................................................................................61
20.2 USB Electrical Characteristics ................................................................................................................63
20.3 CLK30 Clock Specification .....................................................................................................................65
21 Physical Markings ............................................................................................................................................. 65
22 Outline Diagram ................................................................................................................................................ 66
22.1 128-Pin TQFP .........................................................................................................................................66
22.2 161-Ball FSBGA .....................................................................................................................................67
23 Ordering Information ......................................................................................................................................... 68
24 Applicable Documents and Specifications ........................................................................................................ 68
Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Page
USS2000 Block Diagram ......................................................................................................................... 7
USS2000 Pin Diagram ............................................................................................................................ 8
Bottom View of USS2000 161-Ball FSBGA Package ........................................................................... 10
Standard System Configuration ............................................................................................................. 16
Typical Board Connection for Both Power Regulator Enable Polarities ................................................ 56
USB Transceiver Connection ................................................................................................................ 56
Crystal Circuitry ..................................................................................................................................... 57
NAND Tree Logic Structure ................................................................................................................... 60
Clock Waveforms .................................................................................................................................. 61
Tables
Page
Table 1. Numeric Pin Cross Reference .................................................................................................................. 9
Table 2. Ball Cross Reference by Signal .............................................................................................................. 11
Table 3. Ball Cross Reference by Ball Position .................................................................................................... 12
Table 4. PCI Signals ............................................................................................................................................. 13
Table 5. USB Port Signals .................................................................................................................................... 14
Table 6. Legacy Support Signals .......................................................................................................................... 15
Table 7. Chip Test Signals .................................................................................................................................... 15
Table 8. PCI Bus Configuration Memory Summary .............................................................................................. 17
Table 9. Vendor ID Register (00h—01h) ............................................................................................................... 19
Table 10. Device ID Register (02h—03h) ............................................................................................................. 19
Table 11. Command Register (04h—05h) ............................................................................................................ 19
Table 12. Status Register (06h—07h) ................................................................................................................... 19
Table 13. Revision ID Register (08h) .................................................................................................................... 20
Table 14. Class Code Register (09h—0Bh) .......................................................................................................... 20
Table 15. Cache Line Size Register (0Ch) ........................................................................................................... 20
Table 16. Latency Timer Register (0Dh) ............................................................................................................... 20
Table 17. Header Type Register (0Eh) ................................................................................................................. 20
Table 18. BIST Register (0Fh) .............................................................................................................................. 20
Table 19. Base Address Register 0 (10h—13h) ................................................................................................... 21
Table 20. Base Address Register 1, 2, 3, 4, 5 (14h—17h), (18h—1Bh), (1Ch—1Fh), (20h—23h), (24h—27h) .. 21
Table 21. Cardbus CIS Pointer Register (28h—2Bh) ........................................................................................... 21
Agere Systems Inc.
3
USS2000 Four-Port
USB2.0 PCI-to-USB Host Controller
Data Sheet
November 2006
Table of Contents
(continued)
Tables
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
4
Page
Subsystem Vendor ID Register (2Ch—2Dh) .........................................................................................
Subsystem ID Register (2Eh—2Fh) ......................................................................................................
Expansion ROM Base Address Register (30h—33h) ...........................................................................
Capabilities Pointer Register (34h) .......................................................................................................
Interrupt Line Register (3Ch) ................................................................................................................
Interrupt Pin Register (3Dh) ..................................................................................................................
Min_Gnt Register (3Eh) ........................................................................................................................
Max_Lat Register (3Fh) ........................................................................................................................
Wake-Up Enable Register .....................................................................................................................
Special-Vendor Write Capability Register .............................................................................................
Capabilities Identifier (Cap_ID) Register ...............................................................................................
Next Item Pointer Register ....................................................................................................................
Power Management Capabilities Register ............................................................................................
Power Management Control/Status Register ........................................................................................
Power Management Control/Status Bridge ...........................................................................................
Power Management Data Register .......................................................................................................
Power Consumption/Dissipation Reporting ..........................................................................................
Serial Bus Release Number ..................................................................................................................
Frame Length Adjust Register ..............................................................................................................
Port Wake Capability .............................................................................................................................
Microframe Cache .................................................................................................................................
OHCI USB Operational Registers Summary ........................................................................................
HcRevision Register (00h) ....................................................................................................................
HcControl Register (04h) ......................................................................................................................
HcCommandStatus Register (08h) .......................................................................................................
HcInterruptStatus Register (0Ch) ..........................................................................................................
HcInterruptEnable Register (10h) .........................................................................................................
HcInterruptDisable Register (14h) ........................................................................................................
HcHCCA Register (18h) ........................................................................................................................
HcPeriodCurrentED Register (1Ch) ......................................................................................................
HcControlHeadED Register (20h) .........................................................................................................
HcControlCurrentED Register (24h) .....................................................................................................
HcBulkHeadED Register (28h) .............................................................................................................
HcBulkCurrentED Register (2Ch) .........................................................................................................
HcDoneHead Register (30h) .................................................................................................................
HcFmInterval Register (34h) .................................................................................................................
HcFmRemaining Register (38h) ...........................................................................................................
HcFmNumber Register (3Ch) ...............................................................................................................
HcPeriodicStart Register (40h) .............................................................................................................
HcLSThreshold (44h) ............................................................................................................................
HcRhDescriptorA Register (48h) ..........................................................................................................
HcRhDescriptorB Register (4Ch) ..........................................................................................................
HcRhStatus Register (50h) ...................................................................................................................
HcRhPortStatus1 Register (54h) ...........................................................................................................
Legacy Support Registers .....................................................................................................................
Emulated Registers ...............................................................................................................................
HceInput Register (104h) ......................................................................................................................
HceOutput Register (108h) ...................................................................................................................
HceStatus Register (10Ch) ...................................................................................................................
HceControl Register (100h) ..................................................................................................................
Enhanced Host Controller Capability Registers ....................................................................................
21
21
21
22
22
22
22
22
23
23
24
24
25
25
26
26
26
26
27
27
27
28
28
29
29
29
30
31
32
32
32
32
32
32
32
33
33
33
33
33
33
34
34
34
35
35
35
36
36
37
38
Agere Systems Inc.
Data Sheet
November 2006
USS2000 Four-Port
USB2.0 PCI-to-USB Host Controller
Table of Contents
(continued)
Tables
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Page
HCSPARAMS—Host Controller Structural Parameters ........................................................................
HCCPARAMS—Host Controller Capability Parameters .......................................................................
Host Controller Operational Registers ..................................................................................................
USBCMD—USB Command Register Bit Definitions ............................................................................
USBSTS USB Status Register Bit Definitions .......................................................................................
USBINTR—USB Interrupt Enable Register ..........................................................................................
FRINDEX—Frame Index Register ........................................................................................................
PERIODICLISTBASE—Periodic Frame List Base Address Register ...................................................
ASYNCLISTADDR—Current Asynchronous List Address Register ......................................................
CONFIGFLAG—Configure Flag Register Bit Definitions ......................................................................
PORTSC—Port Status and Control ......................................................................................................
PCI Signaling Levels .............................................................................................................................
Test Mode Decode ................................................................................................................................
USS2000 Support for Power Management States ................................................................................
NAND Tree ............................................................................................................................................
Absolute Maximum Ratings ..................................................................................................................
Power Dissipation .................................................................................................................................
Clock and Reset Specifications .............................................................................................................
5 V and 3.3 V PCI Timing Parameters ..................................................................................................
Input Levels for High Speed ..................................................................................................................
Output Levels for High Speed ...............................................................................................................
High-Speed Source Electrical Characteristics ......................................................................................
Full-Speed Source USB Electrical Characteristics ................................................................................
Low-Speed Source USB Electrical Characteristics ...............................................................................
39
40
41
42
44
46
47
48
48
49
50
54
55
58
59
60
61
61
62
63
63
64
64
65
Agere Systems Inc.
5
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