with minimum output capacitance and tight ripple regulation
at very light load. The device is internally compensated and
is stable with any capacitor. No external ESR network is
required for loop stability purpose. The device also
incorporates a power saving scheme that significantly
increases light load efficiency. The regulator integrates a full
protection feature set, including over current protection
(OCP), output overvoltage protection (OVP), short circuit
protection (SCP), output undervoltage protection (UVP) and
thermal shutdown (OTP). It also has UVLO for input rail and
a user programmable soft start.
The SiC47x family is available in 2 A, 4 A, 6 A, 10 A pin
compatible 5 mm by 5 mm lead (Pb)-free power enhanced
MLP55-27L package.
APPLICATIONS
Industrial and automation
Home automation
Industrial and server computing
Networking, telecom, and base station power supplies
Wall transformer regulation
Robotics
High end hobby electronics: remote control cars, planes,
and drones
• Battery management systems
• Power tools
• Vending, ATM, and slot machines
Axis Title
100
97
94
V
IN
= 24 V, V
OUT
= 12 V
V
IN
= 48 V, V
OUT
= 12 V
•
•
•
•
•
•
•
TYPICAL APPLICATION CIRCUIT
Input
4.5 V
DC
to 60 V
DC
C
IN
C
BOOT
Phase
SW
V
OUT
RFU
V
FB
NC
A
GND
P
GND
EN
P
GOOD
BOOT
10000
V
CIN
V
IN
V
DD
V
DRV
SS
I
LIMIT
MODE
2nd line
eff - Efficiency (%)
V
OUT
91
88
85
82
79
76
73
70
0.01
V
IN
= 48 V, V
OUT
= 5 V
V
IN
= 24 V, V
OUT
= 5 V
1000
SiC476
SiC477
SiC478
SiC479
R
up
R
down
C
OUT
100
C
ss
R
MODE
R
fsw
10
0.1
I
OUT
- Output Current (A)
1
Fig. 1 - Typical Application Circuit
Fig. 2 - SiC477 Efficiency vs. Output Current
S19-0439-Rev. A, 27-May-2019
Document Number: 77113
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
1st line
2nd line
f
SW
SiC476, SiC477, SiC478, SiC479
www.vishay.com
PIN CONFIGURATION
27 MODE
27 MODE
23
A
GND
Vishay Siliconix
20
V
OUT
23
A
GND
20
V
OUT
26
V
DD
25
I
LIM
24
f
SW
V
CIN
1
P
GOOD
2
EN 3
BOOT 4
26
V
DD
22
V
FB
21 NC
22
V
FB
25
I
LIM
21 NC
24
f
SW
19
SS
SS
19
RFU 18
P
GND
17
V
DRV
16
GL
15
SW
14
SW
13
SW
12
P
GND
11
P
GND
10
P
GND
9
V
IN
8
V
IN
7
30
P
GND
29
V
IN
28
A
GND
1
V
CIN
2
P
GOOD
3 EN
4 BOOT
28 AGND
18 RFU
17
P
GND
16
V
DRV
15
GL
PHASE 5
PHASE 6
30
VIN
29 PGND
14
SW
13
SW
12
SW
5 PHASE
6 PHASE
P
GND
10
P
GND
11
V
IN
7
V
IN
8
P
GND
9
Fig. 3 - Pin Configuration
PIN DESCRIPTION
PIN NUMBER
1
2
3
4
5, 6
7, 8, 29
9, 10, 11, 17, 30
12, 13, 14
15
16
18
19
20
21
22
23, 28
24
25
26
27
SYMBOL
V
CIN
P
GOOD
EN
BOOT
PHASE
V
IN
P
GND
SW
GL
V
DRV
RFU
SS
V
OUT
NC
V
FB
A
GND
f
SW
I
LIMIT
V
DD
Mode
DESCRIPTION
Supply voltage for internal regulators V
DD
and V
DRV
. This pin should be tied to V
IN
, but can also be
connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required
Enable pin. Tie high / low to enable / disable the IC accordingly. This is a high voltage compatible pin,
can be tied to 55 V
High side driver bootstrap voltage
Return path of high side gate driver
Power stage input voltage. Drain of high side MOSFET
Power ground
Power stage switch node
Low side MOSFET gate signal
Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, V
DRV
is
the LDO output. Connect a 4.7 μF decoupling capacitor to P
GND
Reserved for future use. Leave this pin floating or place a place-holder for a non-populated 10K
resistor between this pin and V
DD
Set the soft start ramp by connecting a capacitor to A
GND
. An internal current source will charge the
capacitor
Output voltage sense point for internal ripple injection components
No connection internally
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from V
OUT
to A
GND
Analog ground
Set the on-time by connecting a resistor to A
GND
Set the current limit by connecting I
LIMIT
pin to A
GND
, float or V
DD
Bias supply for the IC. V
DD
is an LDO output, connect a 1 μF decoupling capacitor to A
GND
Set various operation modes by connecting a resistor to A
GND
. See specification table for details
S19-0439-Rev. A, 27-May-2019
Document Number: 77113
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC476, SiC477, SiC478, SiC479
www.vishay.com
Vishay Siliconix
PACKAGE
PowerPAK
®
MLP55-27L
Reference board
PowerPAK
®
MLP55-27L
Reference board
PowerPAK
®
PowerPAK
®
MLP55-27L
Reference board
MLP55-27L
Reference board
SiC479
SiC478
SiC477
MARKING CODE
SiC476
ORDERING INFORMATION
PART NUMBER
SiC476ED-T1-GE3
SiC476EVB-D
SiC477ED-T1-GE3
SiC477EVB-D
SiC478ED-T1-GE3
SiC478EVB-E
SiC479ED-T1-GE3
SiC479EVB-E
PART MARKING INFORMATION
=
pin 1 indicator
part number code
Siliconix
logo
ESD
symbol
assembly factory code
year code
week code
lot code
P/N
LL
FYWW
P/N =
=
=
F
Y
WW
LL
=
=
=
=
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
V
CIN
, V
IN
EN
SW / PHASE
V
DRV
V
DD
SW / PHASE (AC)
BOOT
A
GND
to P
GND
All other pins
Temperature
Junction temperature
Storage temperature
Power Dissipation
Thermal resistance from junction to ambient
Thermal resistance from junction to case
ESD Protection
Electrostatic discharge protection
Human body model, JESD22-A114
Charged device model, JESD22-A101
2000
500
V
12
2
°C/W
T
J
T
STG
-40 to +150
-65 to +150
°C
Reference to A
GND
CONDITIONS
Reference to P
GND
Reference to P
GND
Reference to P
GND
Reference to P
GND
Reference to A
GND
100 ns
LIMITS
-0.3 to 60
-0.3 to 55
-0.3 to 60
-0.3 to 6
-0.3 to V
DRV
+ 0.3
-10 to 66
-0.3 to V
PHASE
+ V
DRV
-0.3 to 0.3
-0.3 to V
DD
+ 0.3
V
UNIT
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
S19-0439-Rev. A, 27-May-2019
Document Number: 77113
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC476, SiC477, SiC478, SiC479
www.vishay.com
Vishay Siliconix
MIN.
4.5
TYP.
-
-
-
5
5.3
-
-40 to +105
-40 to +125
MAX.
55
55
55
5.25
5.55
0.92 x V
IN
V
UNIT
RECOMMENDED OPERATING CONDITIONS
(all voltages referenced to GND = 0 V)
PARAMETER
Input voltage (V
IN
)
Control input voltage (V
CIN
)
Enable (EN)
Bias supply (V
DD
)
Drive supply voltage (V
DRV
)
Output voltage (V
OUT
)
Temperature
Recommended ambient temperature
Operating junction temperature
°C
(1)
4.5
0
4.75
4.75
0.8
Note
(1)
For input voltages below 5 V, provide a separate supply to V
CIN
of at least 5 V to prevent the internal V
DD
rail UVLO from triggering
ELECTRICAL SPECIFICATIONS
(V
IN
= V
CIN
= 48 V, T
J
= -40 °C to +125 °C, unless otherwise stated)
PARAMETER
Power Supplies
V
IN
= V
CIN
= 6 V to 55 V,
V
EN
= 5 V, not switching
V
IN
= V
CIN
= 5 V,
V
EN
= 5 V, not switching
V
IN
= V
CIN
= 5 V, I
VDD
= 1 mA
4.7
4.7
-
3.75
-
Non-switching, V
FB
> 0.8 V
V
EN
= 0 V
T
J
= 25 °C
T
J
= -40 °C to +125 °C
(1)
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
5
5
150
4
150
-
4
800
800
2
45
-
-
250
3.5
-
15
7
26
11
35
25
45
30
5.3
V
-
-
4.25
-
200
8
804
808
-
100
10
8000
-
6
3
-
-
-
-
-
-
-
-
m
mV
V
mV
μA
V
DD
supply
V
DD
dropout
V
DD
UVLO threshold, rising
V
DD
UVLO hysteresis
Input current
Shutdown current
Controller and Timing
Feedback voltage
V
FB
input bias current
Minimum on-time
t
ON
accuracy
On-time range
Minimum off-time
Soft start current
Zero crossing detection point
Power MOSFETs
High side on resistance
Low side on resistance
High side on resistance
Low side on resistance
High side on resistance
Low side on resistance
High side on resistance
Low side on resistance
V
DD
V
DD_DROPOUT
V
DD_UVLO
V
DD_UVLO_HYST
IV
CIN
IV
CIN_SHDN
-
-
796
792
-
-
-10
100
-
2
V
FB
I
FB
t
ON_MIN.
t
ON_ACCURACY
t
ON_RANGE
t
OFF_MIN.
I
SS
ZCD
R
ON_HS
R
ON_LS
R
ON_HS
R
ON_LS
R
ON_HS
R
ON_LS
R
ON_HS
R
ON_LS
m/V
nA
ns
%
ns
ns
μA
mV
LX-P
GND
SiC476 (10 A),
V
DRV
= 5.3 V, T
A
= 25 °C
SiC477 (6 A),
V
DRV
= 5.3 V, T
A
= 25 °C
SiC478 (4 A),
V
DRV
= 5.3 V, T
A
= 25 °C
SiC479 (2 A),
V
DRV
= 5.3 V, T
A
= 25 °C
-3
-
-
-
-
-
-
-
-
S19-0439-Rev. A, 27-May-2019
Document Number: 77113
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC476, SiC477, SiC478, SiC479
www.vishay.com
Vishay Siliconix
SYMBOL
TEST CONDITIONS
I
LM
tied to V
DD
MIN.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
-
15
1.39
1.17
153
-
-
Power save mode enabled, V
DD
, V
DRV
Pre-reg on
Power save mode disabled, V
DD
, V
DRV
Pre-reg on
Power save mode disabled, V
DRV
Pre-reg
off, V
DD
Pre-reg on, provide external V
DRV
Power save mode enabled, V
DRV
Pre-reg off,
V
DD
Pre-reg on, provide external V
DRV
-
-
-
-
TYP.
13
9.75
6.5
10
7.5
5
6
4.2
3
4
3
2
20
-80
150
35
20
-10
40
6
25
1.4
1.2
200
6
5
2
301
499
1000
MAX.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55
15
35
1.43
1.24
244
-
-
-
-
k
-
-
%
°C
A
UNIT
ELECTRICAL SPECIFICATIONS
(V
IN
= V
CIN
= 48 V, T
J
= -40 °C to +125 °C, unless otherwise stated)
PARAMETER
Fault Protections
SiC476 valley current limit
I
LM
is not connect
I
LM
tied to A
GND
I
LM
tied to V
DD
SiC477 valley current limit
I
OCP
SiC478 valley current limit
I
LM
is not connect
I
LM
tied to A
GND
I
LM
tied to V
DD
I
LM
is not connect
I
LM
tied to A
GND
I
LM
tied to V
DD
SiC479 valley current limit
Output OVP threshold
Output UVP threshold
Over temperature protection
Power Good
Power good output threshold
Power good hysteresis
Power good on resistance
Power good delay time
EN / MODE / Threshold
EN logic high level
EN logic low level
EN logic hysteresis
EN pull down resistance
Mode pull up current
Mode 1
Mode 2
R
MODE
Mode 3
Mode 4
Note
(1)
Guaranteed by design
V
EN_H
V
EN_L
V
EN_HYS
R
EN
I
MODE
V
mV
M
μA
V
FB_RISING_VTH_OV
V
FB_FALLING_VTH_UV
P
GOOD_HYST
R
ON_PGOOD
t
DLY_PGOOD
V
FB
rising above 0.8 V reference
V
FB
falling below 0.8 V reference
%
mV
μs
OVP
UVP
OTP
R
OTP
HYST
I
LM
is not connect
I
LM
tied to A
GND
V
FB
with respect to 0.8 V reference
Rising temperature
Hysteresis
S19-0439-Rev. A, 27-May-2019
Document Number: 77113
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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