3 Volt Intel
®
Advanced+ Stacked Chip
Scale Package Memory
28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3
Preliminary Datasheet
Product Features
■
■
■
■
Flash Memory Plus SRAM
— Reduces Memory Board Space
Required, Simplifying PCB Design
Complexity
Stacked Chip Scale Package Technology
— Smallest Memory Subsystem Footprint
— 16 Mbit Flash + 2 Mbit SRAM:
Area: 8 mm by 10 mm, Height: 1.4 mm
— 32 Mbit Flash + 8 Mbit SRAM:
Area: 8 mm by 14 mm, Height: 1.4 mm
— 32 Mbit Flash + 4 Mbit SRAM,
16 Mbit Flash + 4 Mbit SRAM:
Area: 8 mm by 12 mm, Height: 1.4 mm
Advanced SRAM Technology
— 70 ns Access Time
— Low Power Operation
— Low Voltage Data Retention Mode
Intel
®
Flash Data Integrator (FDI) Software
— Real-Time Data Storage and Code
Execution in the Same Memory Device
— Full Flash File Manager Capability
■
■
■
■
■
Advanced+ Boot Block Flash Memory
— 90 ns 16 Mb Access Time at 2.7 V
— 70 ns 32 Mb Access Time at 2.7 V with
8 Mbit SRAM
— 100 ns 32 Mb Access Time at 2.7 V with
4 Mbit SRAM
— Instant, Individual Block Locking
— 128 bit Protection Register
— 12 V Production Programming
— Ultra Fast Program and Erase Suspend
— Extended Temperature –25 °C to +85 °C
Blocking Architecture
— Block Sizes for Code + Data Storage
— 4-Kword Parameter Blocks (for data)
— 64-Kbyte Main Blocks (for code)
— 100,000 Erase Cycles per Block
Low Power Operation
— Async Read Current: 9 mA
— Standby Current: 7 µA
— Automatic Power Saving Mode
0.18 µm ETOX™ VI Flash Technology
— 28F3208C3
Industry Compatibility
— Sourcing Flexibility and Stability
The 3 Volt Intel
®
Advanced+ Stacked Chip Scale Package (Stacked-CSP) memory delivers a
feature-rich solution for low-power applications. Stacked-CSP memory devices incorporate
flash memory and static RAM in one package with low voltage capability to achieve the smallest
system memory solution form-factor together with high-speed, low-power operations. The flash
memory offers a protection register and flexible block locking to enable next generation security
capability. Combined with the Intel-developed Flash Data Integrator (FDI) software, the
Stacked-CSP memory provides you with a cost-effective, flexible, code plus data storage
solution.
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290666-008
June, 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3 may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation 1999–2001.
*Other brands and names are the property of their respective owners.
PRELIMINARY
28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3
Contents
1.0
Introduction
.................................................................................................................. 1
1.1
1.2
1.3
1.4
Document Conventions ......................................................................................... 1
Product Overview .................................................................................................. 1
Package Ballout .................................................................................................... 2
Signal Definitions................................................................................................... 3
Bus Operation ....................................................................................................... 5
2.1.1 Read......................................................................................................... 5
2.1.2 Output Disable.......................................................................................... 6
2.1.3 Standby .................................................................................................... 6
2.1.4 Flash Reset .............................................................................................. 7
2.1.5 Write ......................................................................................................... 7
Read Array (FFh) .................................................................................................. 7
Read Identifier (90h).............................................................................................. 7
Read Status Register (70h)................................................................................... 8
3.3.1 Clear Status Register (50h)...................................................................... 8
Read Query (98h).................................................................................................. 9
Word Program (40h/10h)....................................................................................... 9
3.5.1 Suspending and Resuming Program (B0h/D0h) ...................................... 9
Block Erase (20h)................................................................................................ 10
3.6.1 Suspending and Resuming Erase (B0h/D0h) ........................................ 10
Instant, Individual Block Locking ......................................................................... 12
3.7.1 Block Locking Operation Summary ........................................................ 12
3.7.2 Locked State .......................................................................................... 13
3.7.3 Unlocked State ....................................................................................... 13
3.7.4 Lock-Down State .................................................................................... 13
3.7.5 Reading a Block’s Lock Status............................................................... 13
3.7.6 Locking Operation during Erase Suspend.............................................. 14
3.7.7 Status Register Error Checking.............................................................. 14
128-Bit Protection Register ................................................................................. 15
3.8.1 Reading the Protection Register ............................................................ 15
3.8.2 Programming the Protection Register (C0h) .......................................... 15
3.8.3 Locking the Protection Register ............................................................. 16
Additional Flash Features.................................................................................... 16
3.9.1 Improved 12 Volt Production Programming ........................................... 16
3.9.2 F-VPP
≤
VPPLK for Complete Protection .............................................. 17
Absolute Maximum Ratings................................................................................. 17
Operating Conditions........................................................................................... 18
Capacitance ........................................................................................................ 18
DC Characteristics ..............................................................................................19
Flash AC Characteristics—Read Operations ...................................................... 23
Flash AC Characteristics—Write Operations ...................................................... 25
2.0
Principles of Operation
............................................................................................ 5
2.1
3.0
Flash Memory Modes of Operation
..................................................................... 7
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
Electrical Specifications
........................................................................................ 17
4.1
4.2
4.3
4.4
4.5
4.6
PRELIMINARY
iii
28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3
4.7
4.8
4.9
4.10
4.11
Flash Erase and Program Timings(1) ................................................................. 26
Flash Reset Operations ...................................................................................... 28
SRAM AC Characteristics—Read Operations(1) ................................................ 29
SRAM AC Characteristics—Write Operations(1, 2) ............................................ 31
SRAM Data Retention Characteristics(1) —Extended Temperature .................. 32
5.0
6.0
Migration Guide Information
............................................................................... 33
System Design Considerations
.......................................................................... 34
6.1
6.2
6.3
6.4
6.5
6.6
Background ......................................................................................................... 34
6.1.1 Flash + SRAM Footprint Integration....................................................... 34
6.1.2 Advanced+ Boot Block Flash Memory Features .................................... 34
Flash Control Considerations .............................................................................. 34
6.2.1 F-RP# Connected to System Reset ....................................................... 35
6.2.2 F-VCC, F-VPP and F-RP# Transition..................................................... 35
Noise Reduction.................................................................................................. 36
Simultaneous Operation...................................................................................... 37
6.4.1 SRAM Operation during Flash “Busy” .................................................... 38
6.4.2 Simultaneous Bus Operations................................................................ 38
Printed Circuit Board Notes................................................................................. 38
System Design Notes Summary ......................................................................... 38
7.0
8.0
Ordering Information
.............................................................................................. 39
Additional Information
........................................................................................... 40
Program/Erase Flowcharts
............................................................................. 41
CFI Query Structure
........................................................................................... 47
Word-Wide Memory Map Diagrams
............................................................. 54
Device ID Table
.................................................................................................... 56
Protection Register Addressing
................................................................... 57
Mechanical and Shipping Media Details
................................................... 58
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Appendix F
iv
PRELIMINARY
28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3
Revision History
Date of
Revision
03/30/99
04/26/99
Version
-001
-002
Original version
Corrected title headings in Appendix B
Removed reference to 8-Mbit devices, Appendix B, Table B7, Device Geometry
Definition
Corrected 4-Mb SRAM I
CC2
specification
Removed extra SRAM standby mode
Clarified
Locking Operations Flowchart
(Appendix A)
Added 16Mbit Flash + 4Mbit SRAM product references
Clarified
Operating Mode
Table (Section 4.1.2)
Clarified “Unlock” in
Command Bus Definitions
Table (Section 5.0)
Updated DC characteristics V
IL
,V
IH
,and I
CCD
(Section 9.4)
Updated AC characteristics t
EHQZ
(Section 9.5)
Updated AC characteristics t
LZ
(Section 9.9)
Removed 3.0-3.3V specifications (Section 9.5 and Section 9.6)
Increased Erase Cycles per Block to 1,000,000
Pinout Update (Figure 1)
Operating Modes clarifications (Table 3)
Clarified product proliferations
Structure/Text of document simplified for readability
Datasheet changed to “Preliminary” status
Changed Erase Cycles per Block to 100,000 (Section 1.2)
Pinout Update (Figure 1)
Added Operating Modes S-UB# and S-LB# (Table 2)
Changed Minimum Temperature Spec from –40°C to –25°C (Section 4.1 and
Table 9)
Added 8-Mb SRAM specifications (Section 4.4,
DC Characteristics,
and Section
4.9)
Changed V
CC1
to V
CC
, Changed S-CS#
1
to S-CS
1
# (Section 4.11)
Added note to Figure 1
Updated Figure 2
Clarified S-UB# and S-LB# functions in Table 2 and Section 2.1
Changed I
CCS
Spec from 20µA to 40µA in Table 10,
DC Characteristics
Changed I
DR
Max spec from 35µA to 6µA in Table 18
Added 70ns and 90ns 0.18µm 28F3208C3 product offerings
Updated Ordering Information
Updated Test Configuration (Figure 5)
Changed I
DR
Max spec for 2 and 4 Mbit SRAM from 6µm to 5µm
Description
06/15/99
08/11/99
-003
-004
01/20/00
-005
08/09/00
-006
01/30/01
-007
06/06/01
-008
PRELIMINARY
v
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