IDT74LVC137A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS
3-LINE TO 8-LINE
DECODER/DEMULTIPLEXER,
WITH ADDRESS LATCHES
FEATURES:
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.635mm pitch QSOP,
0.65mm pitch SSOP, 0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVC137A
DESCRIPTION:
The LVC137A 3-line to 8-line decoder/demultiplexer is built using
advanced dual metal CMOS technology. The LVC137A is designed for
high-performance memory-decoding or data-routing applications requir-
ing very short propagation delay times. In high-performance memory
systems, this decoder minimizes the effects of system decoding. When
employed with high-speed memories utilizing a fast enable circuit, the delay
times of this decoder and the enable time of the memory are usually less
than the typical access time of the memory. This means that the effective
system delay introduced by the decoder is negligible.
When the latch enable (G2A) input is low, the LVC137A acts as a
decoder/demultiplexer. When
G2A
transitions from low to high, the address
present at the inputs (A, B, and C) is stored in the latches. Further address
changes are ignored, provided
G2A
remains high. The output-enable (G1
and
G2B)
inputs control the outputs independently of the select or latch-
enable inputs. All of the outputs are forced high if G1 is low or
G2B
is high.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC137A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Drive Features for LVC137A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
Functional Block Diagram
A
1
15
Y0
14
Y1
13
Select
Inputs
B
2
Y2
12
Y3
D ata
O utputs
Y4
3
11
C
10
Y5
9
Y6
Latch
Enable
G 2A
4
8
Y7
G 2B
G1
5
6
O utput
Enables
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MAY 1999
DSC-4753/1
IDT74LVC137A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
A
B
C
G 2A
G 2B
G
1
Y
7
G ND
1
2
3
4
5
6
7
8
16
15
14
13
SO16-7
SO16-8
12
SO16-9
SO16-10 11
10
9
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
LVC QUAD Link
Max.
– 0.5 to +6.5
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
Unit
V
V
°C
mA
mA
mA
SOIC/ SSOP/ TSSOP/ QSOP
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
PIN DESCRIPTION
Pin Names
G
1
G2A
G2B
Yx
A, B, C
Description
Output Enable
Latch Enable (Active LOW)
Output Enable (Active LOW)
Data Outputs
Select Data Inputs
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
LVC QUAD Link
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
(1)
Latch
Enable
G2A
X
X
L
L
L
L
L
L
L
L
H
Inputs
Output
Enable
G1
G2B
X
H
L
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Select Inputs
Outputs
C
X
X
L
L
L
L
H
H
H
H
X
B
X
X
L
L
H
H
L
L
H
H
X
A
X
X
L
H
L
H
L
H
L
H
X
Y
0
H
H
L
H
H
H
H
H
H
H
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
Outputs corresponding to stored address = L; all other outputs = H
Y
7
H
H
H
H
H
H
H
H
H
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2
IDT74LVC137A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°c to +85°c
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
10
µA
V
mV
µA
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
µA
µA
V
Unit
V
Quiescent Power Supply
Current Variation
One input at V
CC
– 0.6V
other inputs at V
CC
or GND
—
—
500
µA
LVC QUAD Link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
LVC QUAD Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
c
1998 Integrated Device Technology, Inc.
3
DSC-123456
IDT74LVC137A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
V
CC
= 2.5V±0.2V
Symbol
Parameter
C
PD
Power Dissipation Capacitance
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
—
V
CC
= 3.3V±0.3V
Typical
25
Unit
pF
SWITCHING CHARACTERISTICS
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
W
t
SU
t
H
t
SK(0)
Parameter
Propagation Delay
A to B, C to Yx
Propagation Delay
G2A
to Yx
Propagation Delay
G1 or
G2B
to Yx
Pulse Duration,
G2A
Setup Time, at A, B, and C before
G2A↓
Hold Time, at A, B, and C after
G2A↓
Output Skew
(2)
Min.
—
—
—
3
2
1.2
—
(1)
V
CC
= 2.7V
Min.
—
—
—
3
2.1
1.1
—
Max.
6.9
8.5
8.2
—
—
—
—
V
CC
= 3.3V±0.3V
Min.
1
1
1
3
1.9
1.1
—
Max.
6.2
7.8
7.5
—
—
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
V
CC
= 2.5V±0.2V
Max.
—
—
—
—
—
—
—
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC137A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 2.5V ±0.2V
2 x Vcc
Vcc
V
CC
/ 2
150
150
30
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
V
CC
(2)
= 3.3V ±0.3V & 2.7V
6
2.7
1.5
300
300
50
Unit
V
V
V
mV
mV
pF
LVC QUAD Link
SA M E PH AS E
IN PU T TR AN S ITIO N
t
PLH
O U TPU T
t
PLH
O PPO SITE P H AS E
IN PU T TR AN S ITIO N
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LV C Q U A D L in k
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
G enerator
(1, 2)
V
LOAD
O pen
GND
ENABLE AND DISABLE TIMES
EN ABLE
C O N TR O L
IN PU T
t
PZL
t
PLZ
V
LOAD/2
V
T
t
PH Z
V
T
0V
D ISAB LE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
LV C Q U A D L in k
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
L V C Q U A D L in k
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
O U TPU T
SW ITCH
N O R M ALLY
CLO SED
LO W
t
PZH
O U TPU T
SW ITCH
N O R M ALLY
OP EN
H IGH
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
D A TA
IN PU T
TIM IN G
IN PU T
SY N C H RO N O U S
C O N TR O L
LVC QUAD Link
t
SU
t
H
GND
Open
t
REM
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
L V C Q U A D L in k
OUTPUT SKEW - tsk (x)
IN PU T
t
PLH1
t
PH L1
V
IH
V
T
0V
V
OH
AS YN C H RO N O U S
C O N TR O L
t
SU
t
H
PULSE WIDTH
LO W -H IG H -LO W
PU LSE
t
W
H IGH -LO W -H IG H
PU LSE
V
T
LV C Q U A D L in k
O U TP U T 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
O U TP U T 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PL H2
-
t
PLH1
or
t
PH L2
-
t
PHL1
LV C Q U A D L in k
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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