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PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
4-, 8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3
28F008B3, 28F016B3, 28F032B3
Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
12 V V
PP
Fast Production
Programming
2.7 V or 1.65 V I/O Option
Reduces Overall System Power
High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
Optimized Block Sizes
Eight 8-KB Blocks for Data,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks for
Code
Block Locking
V
CC
-Level Control through WP#
Low Power Consumption
10 mA Typical Read Current
Absolute Hardware-Protection
V
PP
= GND Option
V
CC
Lockout Voltage
Extended Temperature Operation
–40 °C to +85 °C
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Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., Voice)
Automated Program and Block Erase
Status Registers
Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles Guaranteed
Automatic Power Savings Feature
Typical I
CCS
after Bus Inactivity
Standard Surface Mount Packaging
48-Ball
µBGA*
Package
48-Lead TSOP Package
40-Lead TSOP Package
Footprint Upgradeable
Upgrade Path for 4-, 8-, 16-, and 32-
Mbit Densities
ETOX™ VI (0.25
µ)
Flash Technology
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The Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a feature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and
interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single
device. Add to this the Intel-developed Flash Data Integrator (FDI) software, and you have a cost-effective,
monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40-
lead and 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s WWW page: http://www.intel.com/design/flash.
July 1998
Order Number: 290580-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997,1998
*
Third-party brands and names are the property of their respective owners
CG-041493
E
PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts ..........................................6
2.2 Block Organization .....................................11
2.2.1 Parameter Blocks ................................11
2.2.2 Main Blocks .........................................11
3.0 PRINCIPLES OF OPERATION .....................11
3.1 Bus Operation ............................................12
3.1.1 Read....................................................13
3.1.2 Output Disable.....................................13
3.1.3 Standby ...............................................13
3.1.4 Deep Power-Down / Reset ..................13
3.1.5 Write....................................................13
3.2 Modes of Operation....................................14
3.2.1 Read Array ..........................................14
3.2.2 Read Identifier .....................................15
3.2.3 Read Status Register ..........................16
3.2.4 Program Mode.....................................16
3.2.5 Erase Mode .........................................17
3.3 Block Locking.............................................20
3.3.1 WP# = V
IL
for Block Locking................20
3.3.2 WP# = V
IH
for Block Unlocking ............20
3.4 V
PP
Program and Erase Voltages ..............20
3.4.1 V
PP
= V
IL
for Complete Protection .......20
SMART 3 ADVANCED BOOT BLOCK
CONTENTS
PAGE
3.5 Power Consumption ...................................20
3.5.1 Active Power .......................................21
3.5.2 Automatic Power Savings (APS) .........21
3.5.3 Standby Power ....................................21
3.5.4 Deep Power-Down Mode.....................21
3.6 Power-Up/Down Operation.........................21
3.6.1 RP# Connected to System Reset ........21
3.6.2 V
CC
, V
PP
and RP# Transitions .............21
3.7 Power Supply Decoupling ..........................22
4.0 ELECTRICAL SPECIFICATIONS..................23
4.1 Absolute Maximum Ratings ........................23
4.2 Operating Conditions..................................24
4.3 Capacitance ...............................................24
4.4 DC Characteristics .....................................25
4.5 AC Characteristics—Read Operations .......28
4.6 AC Characteristics—Write Operations........30
4.7 Program and Erase Timings .......................31
5.0 RESET OPERATIONS ..................................33
6.0 ORDERING INFORMATION..........................34
7.0 ADDITIONAL INFORMATION .......................36
APPENDIX A: Write State Machine
Current/Next States.....................................37
APPENDIX B: Access Time vs.
Capacitive Load...........................................38
APPENDIX C: Architecture Block Diagram ......39
APPENDIX D: Word-Wide Memory Map
Diagrams......................................................40
APPENDIX E: Byte Wide Memory Map
Diagrams......................................................43
APPENDIX F: Program and Erase Flowcharts .45
PRELIMINARY
3
SMART 3 ADVANCED BOOT BLOCK
E
Description
REVISION HISTORY
Number
-001
-002
Original version
Section 3.4,
V
PP
Program and Erase Voltages,
added
Updated Figure 9:
Automated Block Erase Flowchart
Updated Figure 10:
Erase Suspend/Resume Flowchart
(added program to table)
Updated Figure 16:
AC Waveform: Program and Erase Operations
(updated notes)
I
PPR
maximum specification change from ±25
µA
to ±50
µA
Program and Erase Suspend Latency specification change
Updated Appendix A:
Ordering Information
(included 8 M and 4 M information)
Updated Figure, Appendix D:
Architecture Block Diagram
(Block info. in words not
bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V
PP
read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved
Ordering Information
from Appendix to Section 6.0; updated information
Moved
Additional Information
from Appendix to Section 7.0
Updated figure Appendix B,
Access Time vs. Capacitive Load
Updated figure Appendix C,
Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated
Program Flowchart
Updated
Program Suspend/Resume Flowchart
Minor text edits throughout.
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A
1
–A
20
= 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
V
CC
and V
CCQ
absolute maximum specification = 3.7 V (Section 4.1)
Combined I
PPW
and I
CCW
into one specification (Section 4.4)
Combined I
PPE
and I
CCE
into one specification (Section 4.4)
Max Parameter Block Erase Time (t
WHQV2
/t
EHQV2
) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (t
WHQV3
/t
EHQV3
) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (t
WHRH2
/t
EHRH2
) changed to 5 µs typical and 20 µs
maximum (Section 4.7)
Ordering Information
updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA
package diagrams corrected (Figures 3 and 4)
I
PPD
test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA
package top side mark information added (Section 6)
-003
-004
-005
4
PRELIMINARY
E
1.0
SMART 3 ADVANCED BOOT BLOCK
INTRODUCTION
1.1
Smart 3 Advanced Boot Block
Flash Memory Enhancements
This datasheet contains the specifications for the
Advanced Boot Block flash memory family, which is
optimized for low power, portable systems. This
family of products features 1.65 V–2.5 V or 2.7 V–
3.6 V I/Os and a low V
CC
/V
PP
operating range of
2.7 V–3.6 V for read, program, and erase
operations. In addition this family is capable of fast
programming at 12 V. Throughout this document,
the term “2.7 V” refers to the full voltage range
2.7 V–3.6 V (except where noted otherwise) and
“V
PP
= 12 V” refers to 12 V ±5%. Section 1.0 and
2.0 provide an overview of the flash memory family
including applications, pinouts and pin descriptions.
Section 3.0 describes the memory organization and
operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally,
Sections 6.0 and 7.0 provide ordering and other
reference information.
The Smart 3 Advanced Boot Block flash memory
features
•
•
•
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
Program Suspend to Read command
V
CCQ
input of 1.65 V–2.5 V on all I/Os. See
Figures 1 through 4 for pinout diagrams and
V
CCQ
location
Maximum program and erase time specification
for improved data storage.
•
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
V
CC
Read Voltage
V
CCQ
I/O Voltage
V
PP
Program/Erase Voltage
Bus Width
Speed
Memory Arrangement
28F008B3, 28F016B3,
28F032B3
(1)
28F400B3
(2),
28F800B3,
28F160B3, 28F320B3
Reference
Section 4.2, 4.4
Section 4.2, 4.4
Section 4.2, 4.4
Table 3
Section 4.5
Section 2.2
2.7 V– 3.6 V
1.65 V–2.5 V or 2.7 V– 3.6 V
2.7 V– 3.6 V or 11.4 V– 12.6 V
8-bit
16 bit
80 ns, 90 ns, 100 ns, 110 ns
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit),
4096 Kbit x 8 (32 Mbit)
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit)
2048 Kbit x 16 (32 Mbit)
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks
and
Seven 64-Kbyte blocks (4-Mbit) or
Fifteen 64-Kbyte blocks (8-Mbit) or
Thirty-one 64-Kbyte main blocks (16-Mbit)
Sixty-three 64-Kbyte main blocks (32-Mbit)
WP# locks/unlocks parameter blocks
All other blocks protected using V
PP
Extended: –40
°C
to +85
°C
100,000 cycles
40-lead TSOP
(1)
, 48-Ball
µBGA*
CSP
(2)
48-Lead TSOP, 48-Ball
µBGA
CSP
(2)
Section 2.2
Appendix D
Locking
Operating Temperature
Program/Erase Cycling
Packages
Section 3.3
Table 8
Section 4.2, 4.4
Section 4.2, 4.4
Figure 3, Figure 4
NOTES:
1.
4-Mbit and 32-Mbit density not available in 40-lead TSOP.
2.
4-Mbit density not available in
µBGA*
CSP.
PRELIMINARY
5
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