Latch-up Current..................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40°C to +85°C
V
CC
[8]
4.5V to 5.5V
Speed
45 ns
55 ns
Automotive –40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB2
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-down
Current—CMOS
Inputs
Test Conditions
I
OH
= –1 mA
I
OL
= 2.1 mA
V
CC
= 4.5V
V
CC
= 4.5V
2.2
–0.5
–1
–1
11
1.3
1
45 ns
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
16
2
4
2.2
–0.5
–1
–1
11
1.3
1
Typ.
[3]
Max.
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
35
4
30
µA
55 ns
Typ.
[3]
Max.
Unit
V
V
V
V
µA
µA
mA
V
CC
= 4.5V to 5.5V
Input LOW voltage V
CC
= 4.5V to 5.5V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output
Disabled
f = f
MAX
= 1/t
RC
V
CC
= V
CCmax
I
OUT
= 0 mA
f = 1 MHz
CMOS levels
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CCmax
Capacitance
(for all packages)
[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
10
10
Unit
pF
pF
Thermal Resistance
Parameter
Θ
JA
Θ
JC
Description
Test Conditions
SOIC
Package
48.67
25.86
STSOP
Package
32.56
3.59
TSOP
Package
33.01
3.42
Unit
°C/W
°C/W
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch,
[9]
two-layer printed circuit board
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
[9]
Notes
6. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
7. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100-µs ramp time from 0 to V
CC
(min) and 200-µs wait time after V
CC
stabilization.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05485 Rev. *D
Page 3 of 12
CY62128E
MoBL
®
AC Test Loads and Waveforms
V
CC
OUTPUT
R1
3.0V
R2
ALL INPUT PULSES
90%
90%
10%
10%
Fall Time = 1 V/ns
30 pF
INCLUDING
JIG AND
SCOPE
GND
Rise Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Value
1800
990
639
1.77
Data Retention Characteristics
(Over the Operating Range)
[10]
Parameter
V
DR
I
CCDR
t
CDR[10]
t
R[11]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= V
DR
CE > V
CC
– 0.2V,
Industrial
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V Automotive
0
t
RC
Conditions
Min.
2
4
30
Typ.
[3]
Max.
Unit
V
µA
µA
ns
ns
Data Retention Waveform
[10,11]
V
CC
V
CC(min)
t
CDR
DATA RETENTION MODE
V
DR
> 2 V
V
CC(min)
t
R
CE
Notes
10. When CE is LOW, CE
1
is LOW and CE
2
is HIGH. When CE is HIGH, CE
1
is HIGH or CE
2
is LOW.
11. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
> 100
µs.
Document #: 38-05485 Rev. *D
Page 4 of 12
CY62128E
MoBL
®
Switching Characteristics
Over the Operating Range
[10, 12]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to
High-Z
[13, 14]
10
WE HIGH to Low-Z
[13]
45
35
35
0
0
35
25
0
18
10
55
40
40
0
0
40
25
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[13]
OE HIGH to High
CE HIGH to High
Z
[13, 14]
[13]
Description
45 ns
Min.
45
45
10
45
22
5
18
10
18
0
45
0
10
5
10
Max.
Min.
55
55 ns
Max.
Unit
ns
55
55
25
20
20
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Low Z
Z
[13, 14]
CE LOW to Power-up
CE HIGH to Power-down
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
14. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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