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TSB42AA9/TSB42AA9I
StorageLynx 1394 Link Layer Controller for
ATA/ATAPI Storage Products
Data Manual
July 2002
MSDS 1394
SLLS453B
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright
2002, Texas Instruments Incorporated
Contents
Section
1
Title
Page
1–1
1–1
1–1
1–2
1–2
1–3
1–4
2–1
2–1
2–1
2–1
2–3
2–3
2–4
2–4
2–5
2–5
2–5
2–5
2–5
2–6
2–6
2–6
2–6
2–6
2–7
2–7
2–8
3–1
3–1
3–2
3–2
3–2
3–3
3–3
3–5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Terminal Assignments/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
Chapter References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
IEEE 1394a Link Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Receive Packet Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Transmit Packetizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
SBP-2 Transport Protocol Engine . . . . . . . . . . . . . . . . . . . . .
2.2.4.1
Management Agent . . . . . . . . . . . . . . . . . . . . . .
2.2.4.2
Command Agent . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4.3
Data Transfer Control . . . . . . . . . . . . . . . . . . . .
2.2.5
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.1
Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.2
Control FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
Embedded 8052 Processor . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7
Internal ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8
Configuration ROM Fast Access Storage
(Parameter RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.9
ATA/ATAPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.10
Flash PROM/EPROM Interface . . . . . . . . . . . . . . . . . . . . . . .
2.2.11
2-Wire Serial EEPROM Bus Interface . . . . . . . . . . . . . . . . .
2.3
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Chapter References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Registers (CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
Version Register at 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Reserved Register at 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Control Register at 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Interrupt and Interrupt Mask Register at 0C and 10h . . . . .
3.2.5
Cycle Timer Register at 14h . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
iii
4
5
6
Reserved Register at 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Control Register at 1Ch . . . . . . . . . . . . . . . . . .
Reserved Register at 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PHY Access Register at 24h . . . . . . . . . . . . . . . . . . . . . . . . .
ATA/ATAPI Interface Configuration Register at 28h . . . . . .
ATA/ATAPI Access Register at 2Ch . . . . . . . . . . . . . . . . . . .
FIFO Status Register at 30h . . . . . . . . . . . . . . . . . . . . . . . . . .
1394 Bus Reset Register at 34h . . . . . . . . . . . . . . . . . . . . . .
Taskfile (0) Register at 38h . . . . . . . . . . . . . . . . . . . . . . . . . . .
Taskfile (1) Register at 3Ch . . . . . . . . . . . . . . . . . . . . . . . . . .
Taskfile (2) Register at 40h . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Register at 44h–48h . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Retry/Priority Budget Register at 4Ch . . . .
Control Transmit FIFO: First and Continue
Register at 50h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.20
Control Transmit FIFO: Update Register at 54h . . . . . . . . .
3.2.21
Reserved at 58h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.22
Control Receive FIFO Register at 5C . . . . . . . . . . . . . . . . . .
3.2.23
SBP-2 Control Register at 60h . . . . . . . . . . . . . . . . . . . . . . . .
3.2.24
SBP-2 Status Register at 64h . . . . . . . . . . . . . . . . . . . . . . . .
3.2.25
Parameter Data Register at 60Ch . . . . . . . . . . . . . . . . . . . . .
3.2.26
Parameter Data Register 6Ch . . . . . . . . . . . . . . . . . . . . . . . .
3.2.27
Command Set Dependent Status FIFO: First and
Continue at 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.28
Command Set Dependent Status FIFO: Update at 74h . .
3.2.29
Data FIFO Access Register at 78h . . . . . . . . . . . . . . . . . . . .
3.2.30
Reserved at 7Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Configuration ROM Requirements (All Values in Hex) . . . . . . . . . . . .
4.2
Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
SCSI Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Supported Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
INQUIRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
MODE SENSE (6) and MODE SENSE (10) . . . . . . . . . . . .
5.2.3
READ (6) and READ (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4
READ CAPACITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.5
TEST UNIT READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.6
VERIFY (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.7
WRITE (6) and WRITE (10) . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.8
WRITE BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.9
PASS THROUGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
External Flash PROM/EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.2.18
3.2.19
3–5
3–5
3–6
3–6
3–6
3–7
3–8
3–9
3–9
3–9
3–10
3–10
3–10
3–10
3–11
3–11
3–11
3–11
3–12
3–12
3–13
3–13
3–13
3–14
3–14
4–1
4–1
4–3
5–1
5–1
5–2
5–2
5–2
5–2
5–2
5–2
5–2
5–2
5–3
5–3
6–1
6–1
iv
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