Si5345/44/42 Rev D Data Sheet
10-Channel, Any-Frequency, Any-Output Jitter Attenuator/
Clock Multiplier
These jitter attenuating clock multipliers combine fourth-generation DSPLL
™
and
MultiSynth
™
technologies to enable any-frequency clock generation and jitter attenu-
ation for applications requiring the highest level of jitter performance. These devices
are programmable via a serial interface with in-circuit programmable non-volatile
memory (NVM) so they always power up with a known frequency configuration. They
support free-run, synchronous, and holdover modes of operation, and offer both au-
tomatic and manual input clock switching. The loop filter is fully integrated on-chip,
eliminating the risk of noise coupling associated with discrete solutions. Furthermore,
the jitter attenuation bandwidth is digitally programmable, providing jitter perform-
ance optimization at the application level. Programming the Si5345/44/42 is easy
with Silicon Labs’
ClockBuilder Pro
™
software. Factory preprogrammed devices are
also available.
Applications:
• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards
• Broadcast video
• Test and measurement
• ITU-T G.8262 (SyncE) compliant
25-54 MHz XTAL
XA
OSC
IN0
4 Input
Clocks
IN1
IN2
÷INT
÷INT
÷INT
÷INT
DSPLL
XB
Si5342
MultiSynth
MultiSynth
MultiSynth
MultiSynth
MultiSynth
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Status Flags
I2C / SPI
Status Monitor
Control
NVM
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Si5345
OUT8
OUT9
KEY FEATURES
• Generates any combination of output
frequencies from any input frequency
• Ultra-low jitter of 90 fs rms
• External Crystal: 25 to 54 MHz
• Input frequency range
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Meets G.8262 EEC Option 1, 2 (SyncE)
• Highly configurable outputs compatible with
LVDS, LVPECL, LVCMOS, CML, and HCSL
with programmable signal amplitude
• Si5345: 4 input, 10 output, 64-QFN 9×9 mm
• Si5344: 4 input, 4 output, 44-QFN 7×7 mm
• Si5342: 4 input, 2 output, 44-QFN 7×7 mm
Si5344
Up to 10
Output Clocks
IN3/FB_IN
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Si5345/44/42 Rev D Data Sheet
Features List
1. Features List
The Si5345/44/42 Rev D features are listed below:
• Generates any combination of output frequencies from any in-
put frequency
• Ultra-low jitter of 90 fs rms
• Input frequency range
• Differential: 8 kHz–750 MHz
• LVCMOS: 8 kHz–250 MHz
• Output frequency range
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Programmable jitter attenuation bandwidth: 0.1 Hz to 4 kHz
• Meets G.8262 EEC Option 1, 2 (SyncE)
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Status monitoring (LOS, OOF, LOL)
• Hitless input clock switching: automatic or manual
• Locks to gapped clock inputs
• Free-run and holdover modes
•
•
•
•
•
Optional zero delay mode
Fastlock feature for low nominal bandwidths
Glitchless on the fly output frequency changes
DCO mode: as low as 0.001 ppb step size
Core voltage
• V
DD
: 1.8 V ±5%
• V
DDA
: 3.3 V ±5%
• Independent output clock supply pins
• 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I
2
C or SPI
•
•
•
•
•
•
•
In-circuit programmable with non-volatile OTP memory
ClockBuilder Pro software simplifies device configuration
Si5345: 4 input, 10 output, 64-QFN 9×9 mm
Si5344: 4 input, 4 output, 44-QFN 7×7 mm
Si5342: 4 input, 2 output, 44-QFN 7×7 mm
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
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Si5345/44/42 Rev D Data Sheet
Ordering Guide
2. Ordering Guide
Ordering Part Number
(OPN)
Si5345
Si5345A-D-GM
1, 2
Si5345B-D-GM
1, 2
Si5345C-D-GM
1, 2
Si5345D-D-GM
1, 2
Si5344
Si5344A-D-GM
1, 2
Si5344B-D-GM
1, 2
Si5344C-D-GM
1, 2
Si5344D-D-GM
1, 2
Si5342
Si5342A-D-GM
1, 2
Si5342B-D-GM
1, 2
Si5342C-D-GM
1, 2
Si5342D-D-GM
1, 2
Si5345/44/42-D-EVB
Si5345-D-EVB
Si5344-D-EVB
Si5342-D-EVB
Notes:
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder
Pro software utility. Custom part number format is “Si5345A-Dxxxxx-GM” where “xxxxx” is a unique numerical sequence repre-
senting the preprogrammed configuration.
—
—
—
Evaluation
Board
—
4/2
0.001 to 1028 MHz
0.001 to 350 MHz
0.001 to 1028 MHz
0.001 to 350 MHz
Integer and
Fractional
Integer Only
44-QFN
7×7 mm
–40 to 85 °C
4/4
0.001 to 1028 MHz
0.001 to 350 MHz
0.001 to 1028 MHz
0.001 to 350 MHz
Integer and
Fractional
Integer Only
44-QFN
7×7 mm
–40 to 85 °C
4/10
0.001 to 1028 MHz
0.001 to 350 MHz
0.001 to 1028 MHz
0.001 to 350 MHz
Integer and
Fractional
Integer Only
64-QFN
9×9 mm
–40 to 85 °C
Number of Input/
Output Clocks
Output Clock Frequency Supported Frequency
Range (MHz)
Synthesis Modes
Package
Temperature
Range
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Si5345/44/42 Rev D Data Sheet
Ordering Guide
Figure 2.1. Ordering Part Number Fields
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Si5345/44/42 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5345’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency. Fractional in-
put dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is
controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which
determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth
dividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the
MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency.
3.1 Frequency Configuration
The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory.
The combination of fractional input dividers (P
n
/P
d
), fractional frequency multiplication (M
n
/M
d
), fractional output MultiSynth division
(N
n
/N
d
), and integer output division (R
n
) allows the generation of virtually any output frequency on any of the outputs. All divider values
for a specific frequency plan are easily determined using the ClockBuilder Pro utility.
3.2 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-
tings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always
remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
3.3 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The
DSPLL will revert to its normal loop bandwidth once lock acquisition has completed.
3.4 Modes of Operation
Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or
Holdover Mode. A state diagram showing the modes of operation is shown in
Figure 3.1 Modes of Operation on page 5.
The follow-
ing sections describe each of these modes in greater detail.
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