K4Q170411C, K4Q160411C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high
speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access
time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of
this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is avail-
able in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
•
Part Identification
- K4Q170411C-B(F) (5V, 4K Ref.)
- K4Q160411C-B(F) (5V, 2K Ref.)
• Extended Data Out mode operation
(Fast Page Mode with Extended Data Out)
• Four separate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
Unit : mW
• TTL compatible inputs and outputs
• Early Write or output enable controlled write
2K
605
550
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply
•
Active Power Dissipation
Refresh Cycle
4K
-50
-60
495
440
Speed
FUNCTIONAL BLOCK DIAGRAM
•
Refresh Cycles
Part
NO.
K4Q170411C
K4Q160411C
Refresh
cycle
4K
2K
Refresh period
Normal
64ms
32ms
Refresh Timer
Refresh Control
Row Decoder
Sense Amps & I/O
RAS
CAS0 - 3
W
Control
Clocks
Vcc
Vss
L-ver
128ms
VBB Generator
Data in
Buffer
•
Performance Range
Speed
-50
-60
Refresh Counter
Memory Array
4,194,304 x 4
Cells
DQ0
to
DQ3
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
A0-A11
(A0 - A10)
*1
A0 - A9
(A0 - A10)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Data out
Buffer
OE
Note)
*1
: 2K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
K4Q170411C, K4Q160411C
CMOS DRAM
PIN CONFIGURATION
(Top Views)
• K4Q17(6)0411C-B
• K4Q17(6)0411C-F
V
CC
DQ0
DQ1
W
RAS
*A11(N.C)
CAS0
CAS1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
DQ3
DQ2
CAS3
OE
A9
CAS2
N.C
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
W
RAS
*A11(N.C)
CAS0
CAS1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
DQ3
DQ2
CAS3
OE
A9
CAS2
N.C
A8
A7
A6
A5
A4
V
SS
*A11 is N.C for K4Q160411C (2K Ref. product)
B : 300mil 28 SOJ
F : 300mil 28 TSOP II
Pin Name
A0 - A11
A0 - A10
DQ0 - 3
V
SS
RAS
CAS0~CAS3
W
OE
V
CC
N.C
Pin Function
Address Inputs (4K Product)
Address Inputs (2K Product)
Data In/Out
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5.0V)
No Connection
K4Q170411C, K4Q160411C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN,
V
OUT
V
CC
Tstg
P
D
I
OS
Rating
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
50
CMOS DRAM
Units
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1.0
*1
0.8
Units
V
V
V
V
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
*2 : -2.0/20ns, Pulse width is measured at V
SS
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.5V,
all other input pins not under test=0 Volt)
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-5mA)
Output Low Voltage Level(I
OL
=4.2mA)
Symbol
I
I(L)
I
O(L)
V
OH
V
OL
Min
-5
-5
2.4
-
Max
5
5
-
0.4
Units
uA
uA
V
V
K4Q170411C, K4Q160411C
DC AND OPERATING CHARACTERISTICS
(Continued)
Symbol
Power
Speed
-50
-60
Don′t care
-50
-60
-50
-60
Don′t care
-50
-60
Don′t care
Don′t care
Max
K4Q170411C
90
80
2
1
90
80
80
70
1
250
90
80
300
250
K4Q160411C
110
100
2
1
110
100
90
80
1
250
110
100
300
250
CMOS DRAM
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
mA
mA
mA
uA
uA
I
CC1
Don′t care
Normal
L
Don′t care
I
CC2
I
CC3
I
CC4
Don′t care
Normal
L
Don′t care
L
L
I
CC5
I
CC6
I
CC7
I
CCS
I
CC1
* : Operating Current (RAS and CAS cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS cycling @t
RC
=min.)
I
CC4
* : Hyper Page Mode Current (RAS=V
IL
, CAS, Address cycling @t
HPC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V,
DQ=Don′t care, T
RC
=31.25us(4K/L-ver), 62.5us(2K/L-ver), T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A11=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ3=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Hyper page mode cycle time, t
HPC
.
K4Q170411C, K4Q160411C
CAPACITANCE
(T
A
=25°C, V
CC
=5V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Input capacitance [RAS, CASx, W, OE]
Output capacitance [DQ0 - DQ3]
Symbol
C
IN1
C
IN2
C
DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
See note 1,2)
Test condition : V
CC
=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Symbol
Min
-50
Max
Min
104
140
50
13
25
3
3
3
2
30
50
13
38
8
20
15
5
0
10
0
8
25
0
0
0
10
10
13
8
10K
37
25
10K
50
13
3
3
3
2
40
60
15
45
10
20
15
5
0
10
0
10
30
0
0
0
10
10
15
10
10K
45
30
10K
50
15
60
15
30
-60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19
8,17
8
16
18
18
16
19
25
4,18
10
17
3,4,10
3,4,5,20
3,10
3,20
6,13
3
2
Units
Notes
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
OLZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
84
106
FPGA/CPLD
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