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HY5PS1G1631ALFP-S5: 产品描述DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84; 产品类别存储存储; 文件大小4MB，共36页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/; 标准

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HY5PS1G1631ALFP-S5概述

DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84

HY5PS1G1631ALFP-S5规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	SK Hynix(海力士)
零件包装代码	BGA
包装说明	TFBGA, BGA92,9X21,32
针数	84
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	MULTI BANK PAGE BURST
最长访问时间	0.4 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	400 MHz
I/O 类型	COMMON
交错的突发长度	4,8
JESD-30 代码	R-PBGA-B84
JESD-609代码	e1
长度	17.5 mm
内存密度	1073741824 bit
内存集成电路类型	DDR DRAM
内存宽度	16
功能数量	1
端口数量	1
端子数量	84
字数	67108864 words
字数代码	64000000
工作模式	SYNCHRONOUS
组织	64MX16
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TFBGA
封装等效代码	BGA92,9X21,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260
电源	1.8 V
认证状态	Not Qualified
刷新周期	8192
座面最大高度	1.2 mm
自我刷新	YES
连续突发长度	4,8
最大待机电流	0.01 A
最大压摆率	0.48 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	20
宽度	11 mm

HY5PS1G1631ALFP-S5文档预览

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

1Gb DDR2 SDRAM

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

Revision Details

Rev.

0.1

0.2

0.3

0.4

0.5

Initial data sheet released

Typo corrected

Leakage current spec added and IDD value updated

Removed improper note in ODT DC spec

Added tDS/tDH(single ended strobe) parameter

History

Draft Date

Mar. 2006

May 2006

July 2006

Aug. 2006

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

Contents

1. Description

1.1 Device Features and Ordering Information

1.1.1 Key

Features

1.1.2 Ordering Information

1.1.3 Ordering Frequency

1.2 Pin configuration

1.3 Pin Description

2. Maximum DC ratings

2.1 Absolute Maximum DC Ratings

2.2 Operating Temperature Condition

3. AC & DC Operating Conditions

3.1 DC Operating Conditions

5.1.1 Recommended DC Operating Conditions(SSTL_1.8)

5.1.2 ODT DC Electrical Characteristics

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

3.2.2 Input AC Logic Level

3.2.3 AC Input Test Conditions

3.2.4 Differential Input AC Logic Level

3.2.5 Differential AC output parameters

3.3 Output Buffer Levels

3.3.1 Output AC Test Conditions

3.3.2 Output DC Current Drive

3.3.3 OCD default

characteristics

3.4 IDD Specifications & Measurement Conditions

3.5 Input/Output Capacitance

4. AC Timing Specifications

5. Package Dimensions

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

•

VDD=1.8V

VDDQ=1.8V +/- 0.1V

All inputs and outputs are compatible with SSTL_18 interface

Fully differential clock inputs (CK, /CK) operation

Double data rate interface

Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

Differential Data Strobe (DQS, DQS)

Data outputs on DQS, DQS edges when read (edged DQ)

Data inputs on DQS centers when write(centered DQ)

On chip DLL align DQ, DQS and DQS transition with CK transition

DM mask write data-in at the both rising and falling edges of the data strobe

All addresses and control inputs except data, data strobes and data masks latched on the rising

edges of the clock

Programmable CAS latency 3, 4, 5 and 6 supported

Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

Programmable burst length 4/8 with both nibble sequential and interleave mode

Internal eight bank operations with single pulsed RAS

Auto refresh and self refresh supported

tRAS lockout supported

8K refresh cycles /64ms

JEDEC standard 68ball FBGA(x4/x8) , 92ball FBGA(x16)

Full strength driver option controlled by EMRS

On Die Termination supported

Off Chip Driver Impedance Adjustment supported

Read Data Strobe supported (x8 only)

Self-Refresh High Temperature Entry

Ordering Information

Part No.

HY5PS1G431A(L)FP-X*

HY5PS1G831A(L)FP-X*

HY5PS1G1631A(L)FP-X*

Configuration Package

256Mx4

128Mx8

64Mx16

92 Ball

68 Ball

Operating Frequency

Grade

-E3

-C4

-Y5

-S5

tCK(ns)

3.75

2.5

tRCD

tRP

Unit

Clk

Note:

-X* is the speed bin, refer to the Operation Frequency table for complete Part No.

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

1.2 Pin Configuration & Address Table

256Mx4 DDR2 Pin Configuration

(Top view: see balls through package)

VDD

VDDQ

VDDL

VSSQ

DQ1

VSSQ

VREF

CKE

VSS

VDDQ

DQ3

VSS

BA1

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A11

DQS

VSSQ

DQ0

VSSQ

A13

VDDQ

VDD

ODT

BA2

BA0

A10

VDD

VSS

VDD

A12

ROW AND COLUMN ADDRESS TABLE

ITEMS

# of Bank

Bank Address

Auto Precharge Flag

Row Address

Column Address

Page size

Rev. 0.5 / Aug 2006

256Mx4

BA0,BA1,BA2

A10/AP

A0 - A13

A0-A9, A11

1 KB

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HY5PS1G1631ALFP-S5相似产品对比

	HY5PS1G1631ALFP-S5	HY5PS1G431AFP-S5	HY5PS1G831AFP-S5	HY5PS1G1631AFP-S5	HY5PS1G431ALFP-S5	HY5PS1G831ALFP-S5
描述	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84	DDR DRAM, 256MX4, 0.4ns, CMOS, PBGA68, FBGA-68	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA68, FBGA-68	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84	DDR DRAM, 256MX4, 0.4ns, CMOS, PBGA68, FBGA-68	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA68, FBGA-68
是否Rohs认证	符合	符合	符合	符合	符合	符合
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	TFBGA, BGA92,9X21,32	TFBGA, BGA68,9X19,32	TFBGA, BGA68,9X19,32	TFBGA, BGA92,9X21,32	TFBGA, BGA68,9X19,32	TFBGA, BGA68,9X19,32
针数	84	68	68	84	68	68
Reach Compliance Code	compliant	unknown	compliant	compliant	compliant	compli
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
最长访问时间	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	400 MHz	400 MHz	400 MHz	400 MHz	400 MHz	400 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	4,8	4,8	4,8	4,8	4,8	4,8
JESD-30 代码	R-PBGA-B84	R-PBGA-B68	R-PBGA-B68	R-PBGA-B84	R-PBGA-B68	R-PBGA-B68
JESD-609代码	e1	e1	e1	e1	e1	e1
长度	17.5 mm	17.5 mm	17.5 mm	17.5 mm	17.5 mm	17.5 mm
内存密度	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bi
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	16	4	8	16	4	8
功能数量	1	1	1	1	1	1
端口数量	1	1	1	1	1	1
端子数量	84	68	68	84	68	68
字数	67108864 words	268435456 words	134217728 words	67108864 words	268435456 words	134217728 words
字数代码	64000000	256000000	128000000	64000000	256000000	128000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
组织	64MX16	256MX4	128MX8	64MX16	256MX4	128MX8
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装等效代码	BGA92,9X21,32	BGA68,9X19,32	BGA68,9X19,32	BGA92,9X21,32	BGA68,9X19,32	BGA68,9X19,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260	260	260	260	260	260
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192	8192
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES
连续突发长度	4,8	4,8	4,8	4,8	4,8	4,8
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	20	20	20	20	20	20
宽度	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm

HY5PS1G1631ALFP-S5

HY5PS1G1631ALFP-S5概述

HY5PS1G1631ALFP-S5规格参数

HY5PS1G1631ALFP-S5文档预览

HY5PS1G1631ALFP-S5相似产品对比

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