HY62QF16803A Series
512Kx16bit full CMOS SRAM
Preliminary
DESCRIPTION
The HY62QF16803A is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
524,288 words by 16bits. The HY62QF16803A
uses high performance full CMOS process
technology and is designed for high speed and
low power circuit technology. It is particularly well-
suited for the high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 1.2V.
Product
Voltage
Speed
No.
(V)
(ns)
HY62QF16803A
2.3~2.7 70/85/100
HY62QF16803A- I
2.3~2.7 70/85/100
Note 1. Blank : Commercial, I : Industrial
2. Current value is max.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(LL/SL-part)
- 1.2V(min) data retention
•
Standard pin configuration
- 48-uBGA
Operation
Current/Icc(mA)
3
3
Standby Current(uA)
LL
SL
30
8
30
8
Temperature
(°C)
0~70
-45~85(I)
PIN CONNECTION
( Top View )
A1,A2
A4,A6~A7
A9
A12
A15~A18
A8
BLOCK DIAGRAM
ADD INPUT
BUFFER
ROW
DECODER
SENSE AMP
I/O1
/LB
/OE A0
A1
A4
A6
A2
NC
COLUMN
DECODER
IO9 /UB A3
IO10 IO11 A5
/CS IO1
IO2 IO3
IO4 Vcc
I/O8
DATA I/O
BUFFER
ADD INPUT
BUFFER
PRE DECODER
A10
A13
A14
A0
A3
A5
Vss IO12 A17 A7
MEMORY ARRAY
512K x 16
WRITE DRIVER
I/O9
BLOCK
DECODER
Vcc IO13 Vss A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
IO16 NC
A18 A8
A12 A13 /WE IO8
A9
A10 A11 NC
ADD INPUT
BUFFER
I/O16
A11
/CS
/OE
/LB
/UB
/WE
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
/UB
Pin Function
Chip Select
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A18
Vcc
Vss
NC
Pin Function
Data Inputs / Outputs
Address Inputs
Power(2.3V~2.7V)
Ground
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.03 /Jun. 2000
Hyundai Semiconductor
HY62QF16803A Series
ORDERING INFORMATION
Part No.
HY62QF16803ALLM
HY62QF16803ASLM
HY62QF16803ASLM-I
HY62QF16803ASLM-I
Speed
70/85/100
70/85/100
70/85/100
70/85/100
Power
LL-part
SL-part
LL-part
SL-part
Temp.
Package
uBGA
uBGA
uBGA
uBGA
I
I
Note 1. Blank : Commercial, I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
T
STG
P
D
T
SOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.2 to 3.6
-0.2 to 4.6
0 to 70
-40 to 85
-55 to 150
1.0
260
•
10
Unit
V
V
°C
°C
°C
W
°C •
sec
Remark
HY62QF16803A
HY62QF16803A-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS
H
X
L
L
L
/WE
X
X
H
H
H
/OE
X
X
H
H
L
/LB
X
H
L
X
L
H
L
L
H
L
/UB
X
H
X
L
H
L
L
H
L
L
Mode
Deselected
Deselected
Output Disabled
Output Disabled
Read
I/O
I/O1~I/O8 I/O9~I/O16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
OUT
High-Z
High-Z
D
OUT
D
OUT
D
OUT
D
IN
High-Z
High-Z
D
IN
D
IN
D
IN
Power
Standby
Standby
Active
Active
Active
L
L
X
Write
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care(V
IH or
V
IL)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.03 /Jun. 2000
2
HY62QF16803A Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.3
0
2.0
-0.3
(1)
Typ.
2.5
0
-
-
Max.
2.7
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.3V~2.7V, T
A
= 0°C to 70°C / -40°C to 85°C (I)
Sym
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Vss < V
IN
< Vcc
Vss < V
OUT
< Vcc, /CS = V
IH
or
/
OE
=
V
IH
or /WE = V
IL,
/
UB
=
V
IH
and /LB = V
IH
/CS = V
IL
, V
IN
= V
IH
or V
IL
I
I/O =
0mA
Cycle Time=Min,100% duty,
I
I/O =
0mA, /CS = V
IL,
V
IN
= V
IH
or V
IL
Cycle time = 1us, 100% duty,
I
I/O =
0mA, /CS < 0.2V, V
IN
<0.2V
/CS = V
IH
/CS > Vcc - 0.2V
I
OL
= 0.5mA
I
OH =
-0.5mA
SL
LL
Min.
-1
-1
Typ
.
-
-
Max.
1
1
Unit
uA
uA
Icc
Operating Power Supply
Current
Average Operating
Current
TTLStandbyCurrent
(TTL Input)
-
-
-
3
30
5
0.3
8
30
0.4
-
mA
mA
mA
mA
uA
uA
V
V
Icc1
I
SB
I
SB1
V
OL
V
OH
-
-
-
-
-
2.0
-
-
-
8
-
-
Standby Current
(CMOS Input)
Output Low Voltage
Output High Voltage
Note :
1. Typical values are at Vcc = 2.3V~2.7V, T
A
= 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f = 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance(Add, /CS, /WE, /OE)
C
OUT
Output Capacitance(I/O)
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.03 /Jun. 2000
3
HY62QF16803A Series
AC CHARACTERISTICS
Vcc = 2.3V~2.7V, T
A
= 0°C to 70°C/ -40°C to 85°C (I), unless otherwise specified
-70
-85
#
Symbol Parameter
Min.
Max. Min.
Max.
READ CYCLE
1
tRC
Read Cycle Time
70
-
85
-
2
tAA
Address Access Time
-
70
-
85
3
tACS
Chip Select Access Time
-
70
-
85
4
tOE
Output Enable to Output Valid
-
40
-
45
5
tBA
/LB, /UB Access Time
-
70
-
85
6
tCLZ
Chip Select to Output in Low Z
10
-
10
-
7
tOLZ
Output Enable to Output in Low Z
5
-
5
-
8
tBLZ
/LB, /UB Enable to Output in Low Z
5
-
5
-
9
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
10 tOHZ
Out Disable to Output in High Z
0
30
0
30
11 tBHZ
/LB, /UB Disable to Output in High Z
0
30
0
30
12 tOH
Output Hold from Address Change
10
-
10
-
WRITE CYCLE
13 tWC
Write Cycle Time
70
-
85
-
14 tCW
Chip Selection to End of Write
60
-
70
-
15 tAW
Address Valid to End of Write
60
-
70
-
16 tBW
/LB, /UB Valid to End of Write
60
-
70
-
17 tAS
Address Set-up Time
0
-
0
-
18 tWP
Write Pulse Width
50
-
55
-
19 tWR
Write Recovery Time
0
-
0
-
20 tWHZ
Write to Output in High Z
0
25
0
30
21 tDW
Data to Write Time Overlap
30
-
35
-
22 tDH
Data Hold from Write Time
0
-
0
-
23 tOW
Output Active from End of Write
5
-
5
-
-10
Min
Max.
100
-
-
-
-
20
5
5
0
0
0
15
100
80
80
80
0
75
0
0
45
0
10
-
100
100
50
100
-
-
-
30
30
30
-
-
-
-
-
-
-
-
35
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
T
A
= 0°C to 70°C(Commercial)/ -40°C to 85°C (I), unless otherwise specified
PARAMETER
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.1V
Output Load
CL = 30pF + 1TTL Load
AC TEST LOADS
V
TM
= 2.3V
3067 Ohm
D
OUT
CL(1)
3345 Ohm
Note
1. Including jig and scope capacitance
Rev.03 /Jun. 2000
4
HY62QF16803A Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
ADDR
tAA
tACS
/CS
tCHZ
(3)
tBA
/UB ,/ LB
tOE
tOLZ
(3)
tBLZ
(3)
tCLZ
(3)
Data Valid
tBHZ
(3)
tOH
tRC
/OE
tOHZ
(3)
Data
Out
High-Z
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
Data
Out
Previous Data
Data Valid
tOH
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tACS
tCLZ(3)
Data
Out
Data Valid
tCHZ(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1
are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.03 /Jun. 2000
5
FPGA/CPLD
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