HY62U8100B Series
128Kx8bit CMOS SRAM
DESCRIPTION
The HY62U8100B is a high speed, low power and
1M bit CMOS SRAM organized as 131,072 words
by 8bit. The HY62U8100B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particulary well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(LL-part)
-. 2.0V(min) data retention
•
Standard pin configuration
-. 32 - SOP - 525mil
-. 32 - TSOP-I - 8X20(Standard and Reversed)
-. 32 - sTSOP-I - 8X13.4
(Standard and Reversed)
Product
No.
HY62U8100B
HY62U8100B-E
HY62U8100B-I
Voltage
(V)
2.7~3.3
2.7~3.3
2.7~3.3
Speed
(ns)
85/100/120
85/100/120
85/100/120
Operation
Current/Icc(mA)
5
5
5
Standby Current(uA)
LL
10
15
15
Temperature
(°C)
0~70
-25~85(E)
-40~85(I)
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
PIN CONNECTION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
Vcc
A15
CS2
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
A16
NC
Vcc
A15
CS2
/WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
DQ4
DQ5
DQ6
DQ7
DQ8
/CS1
A10
/OE
SOP
sTSOP-I / TSOP-I
( Standard )
sTSOP-I / TSOP-I
(Reversed)
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
A0 ~ A16
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Address Inputs
Data Inputs / Outputs
Power(2.7V~3.3V)
Ground
A0
BLOCK DIAGRAM
ROW
DECODER
SENSE AMP
I/O1
ADD INPUT
BUFFER
BUFFER
COLUMN
DECODER
MEMORY ARRAY
128K x 8
WRITE DRIVER
A16
I/O8
/CS1
LOGIC
CS2
/OE
/WE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.10 / Jun.00
Hyundai Semiconductor
HY62U8100B Series
ORDERING INFORMATION
Part No.
HY62V8100BLLG
HY62U8100BLLT1
HY62U8100BLLR1
HY62U8100BLLST
HY62U8100BLLSR
HY62V8100BLLG-E
HY62U8100BLLT1-E
HY62U8100BLLR1-E
HY62U8100BLLST-E
HY62U8100BLLSR-E
HY62V8100BLLG-I
HY62U8100BLLT1-I
HY62U8100BLLR1-I
HY62U8100BLLST-I
HY62U8100BLLSR-I
Speed
70/85/100
85/100/120
85/100/120
85/100/120
85/100/120
70/85/100
85/100/120
85/100/120
85/100/120
85/100/120
70/85/100
85/100/120
85/100/120
85/100/120
85/100/120
Power
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
Temp.
Package
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
smaller TSOP-I(Standard)
smaller TSOP-I(Reversed)
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
Smaller TSOP-I(Standard)
Smaller TSOP-I(Reversed)
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
Smaller TSOP-I(Standard)
Smaller TSOP-I(Reversed)
E
E
E
E
E
I
I
I
I
I
Note 1. Blank : Commercial, E : Extended, I : Industrial
ABSOLUTE MAXIMUM RATING (1)
Symbol
Vcc, V
IN,
V
OUT
T
A
Parameter
Power Supply, Input/Output Voltage
Operating Temperature
Rating
-0.3 to 4.6
0 to 70
-25 to 85
-40 to 85
-65 to 125
1.0
50
260
•
10
Unit
V
°C
°C
°C
°C
W
mA
°C•sec
Remark
HY62U8100B
HY62U8100B-E
HY62U8100B-I
T
STG
P
D
I
OUT
T
SOLDER
Storage Temperature
Power Dissipation
Data Output Current
Lead Soldering Temperature & Time
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
Mode
Deselected
Deselected
Output Disabled
Read
Write
I/O
High-Z
High-Z
High-Z
Data Out
Data In
Power
Standby
Standby
Active
Active
Active
Note :
1. H=V
IH
, L=V
IL
, X=don't care( V
IH or
V
IL )
Rev.10 / Jun.00
2
HY62U8100B Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
2.2
-0.3
(1)
Typ.
3.0
0
-
-
Max.
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note :
1. V
IL
= -1.5V for pulse width less than 30ns and not 100% tested
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.7V~3.3V, T
A
= 0°C to 70°C / -25°C to 85°C (E) / -40¡
É
85¡
É
I), unless otherwise specified
to
(
Symbol
Parameter
Test Condition
Min. Typ. Max.
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
I
LO
Output Leakage Current
Vss <V
OUT
< Vcc, /CS1 = V
IH
or
-1
-
1
CS2 = V
IL
or
/
OE
=
V
IH
or /WE =
V
IL
Icc
Operating Power Supply
/CS1 = V
IL
, CS2 = V
IH,
-
-
5
Current
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
I
CC1
Average Operating
/CS1 = V
IL
, CS2 = V
IH
,
-
-
30
Current
VIN = V
IH
or V
IL
Cycle Time = Min, 100% duty,
I
IO
= 0mA
I
SB
TTL Standby Current
/CS1 = V
IH
or CS2 = V
IL
-
-
0.5
(TTL Input)
I
SB1
Standby
HY62U8100B
/CS1 > Vcc - 0.2V
-
0.5
10
Current
HY62U8100B-E CS2 < 0.2V or
-
0.5
15
(CMOS Input)
HY62U8100B-I
CS2 > Vcc - 0.2V
-
0.5
15
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
OH
Output High Voltage
I
OH =
-1.0mA
2.2
-
-
Note : Typical values are at Vcc = 3.0V, T
A
= 25°C
Unit
uA
uA
mA
mA
mA
uA
uA
uA
V
V
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
6
8
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.10 / Jun.00
3
HY62U8100B Series
AC CHARACTERISTICS
Vcc = 2.7V~3.3V, T
A
= 0°C to 70°C / -25°C to 85°C (E) / -40¡
É
85¡
É
I), unless otherwise specified
to
(
-85
-10
-12
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
tRC
Read Cycle Time
85
-
100
-
120
-
2
tAA
Address Access Time
-
85
-
100
-
120
3
tACS
Chip Select Access Time
-
85
-
100
-
120
4
tOE
Output Enable to Output Valid
-
45
-
50
-
60
5
tCLZ
Chip Select to Output in Low Z
10
-
20
-
20
-
6
tOLZ
Output Enable to Output in Low Z
5
-
5
-
10
-
7
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
0
40
8
tOHZ
Out Disable to Output in High Z
0
30
0
30
0
40
9
tOH
Output Hold from Address Change
10
-
15
-
15
-
WRITE CYCLE
10 tWC
Write Cycle Time
85
-
100
-
120
-
11 tCW
Chip Selection to End of Write
70
-
80
-
100
-
12 tAW
Address Valid to End of Write
70
-
80
-
100
-
13 tAS
Address Set-up Time
0
-
0
-
0
-
14 tWP
Write Pulse Width
55
-
75
-
85
-
15 tWR
Write Recovery Time
0
-
0
-
0
-
16 tWHZ
Write to Output in High Z
0
30
0
35
0
40
17 tDW
Data to Write Time Overlap
40
-
45
-
50
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
5
-
10
-
10
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
T
A
= 0°C to 70°C / -25°C to 85°C (E) / -40¡
É
85¡
É
I), unless otherwise specified
to
(
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 100pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : 1 Including jig and scope capacitance
Rev.10 / Jun.00
4
HY62U8100B Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tACS
/CS1
tOH
CS2
tCHZ
(3)
/OE
tOLZ
(3)
Data
Out
High-Z
tCLZ
(3)
Data Valid
tOE
tOHZ
(3)
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
Data
Out
Previous Data
Data Valid
tOH
READ CYCLE 3(Note 1,2,4)
/CS1
CS2
tACS
tCLZ
(3)
Data
Out
Data Valid
tCHZ
(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low /CS1 and CS2 are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev.10 / Jun.00
5
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