®
74LVX574
LOW VOLTAGE OCTAL D-TYPE FLIP FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 125 MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOWPOWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
= 25
o
C
LOWNOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX574M
74LVX574T
outputs will be set to logic state that were setup
at the D inputs.
While the (OE) input is low, the 8 outputs will be
in al normal logic state (high or low logic level)
and while high level, the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop, that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumpion.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX574 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
1/10
74LVX574
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 3, 4,
5, 6, 7,
8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
NAME AND FUNCT ION
3 State Output Enable
Input (Active LOW)
Data Inputs
Q0 to Q7
3 State Outputs
CLOCK
GND
V
CC
Clock Input (LOW to
HIGH, edge triggered)
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE
H
L
L
L
X:Don’t Care
Z: High Impedance
OUT PUTS
D
X
X
L
H
Q
Z
NO CHANGE
L
H
CK
X
LOGIC DIAGRAMS
2/10
74LVX574
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
o
o
I
CC
or I
GND
DC V
CC
or Ground Current
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Input Voltage
Output Voltage
Operating Temperature:
Input Rise and Fall Time (V
CC
= 3V) (note 2)
Parameter
Supply Voltage (note 1)
Valu e
2 to 3.6
0 to 5.5
0 to V
CC
-40 to +85
0 to 100
Unit
V
V
V
o
C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
3/10
74LVX574
DC SPECIFICATIONS
Symb ol
Parameter
V
CC
(V)
V
IH
High Level Input Voltage
2.0
3.0
3.6
V
IL
Low Level Input Voltage
2.0
3.0
3.6
V
OH
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage Current
3 State Output Leakage
Current
Quiescent Supply
Current
2.0
3.0
3.0
V
OL
2.0
3.0
3.0
I
I
I
OZ
I
CC
3.6
3.6
3.6
V
I
=
V
IH
or
V
IL
V
I
=
V
IH
or
V
IL
(*)
(* )
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
T yp.
Max.
-40 to 85 C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.0
0.0
0.1
0.1
0.36
±0.1
±0.25
4
0.1
0.1
0.44
±1
±2.5
40
Max.
o
Un it
V
V
I
O
=-50
µA
I
O
=-50
µA
I
O
=-4 mA
I
O
=50
µ
A
I
O
=50
µA
I
O
=4 mA
1.9
2.9
2.58
2.0
3.0
V
V
µA
µA
µA
V
I
= 5V or GND
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= V
CC
or GND
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
V
CC
(V)
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
Dynamic Low Voltage
Input (note 1, 3)
3.3
-0.8
3.3
3.3
C
L
= 50 pF
0.8
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
T yp.
0.3
-0.3
2
Max.
0.8
-40 to 85 C
Min.
Max.
o
Un it
V
1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
). f=1MHz
4/10
74LVX574
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
=3 ns)
Symb ol
Parameter
T est Con ditio n
V
CC
C
L
(V)
(p F)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
2.7
(*)
t
PLH
t
PHL
Propagation Delay Time
CK to Q
15
50
15
50
15
50
15
50
15
50
15
50
15
50
15
50
15
50
15
50
50
50
Valu e
T
A
= 25 C
-40 to
Min. T yp. Max. Min.
9.2
14.5
1.0
11.5 18.0
1.0
o
Un it
85 C
Max.
17.5
21.0
15.5
19.0
18.5
22.0
15.0
18.5
22.0
17.0
7.5
5.0
5.0
3.5
1.5
1.5
o
ns
t
PZL
t
PZH
Output Enable Time
R
L
= 1 k
Ω
t
PLZ
t
PHZ
t
w
t
s
t
h
f
MAX
Output Disable Time
Clock pulse Width, HIGH
Setup Time D to CK
HIGH or LOW
Hold Time D to CK
HIGH or LOW
Maximum Clock
Frequency
R
L
= 1 k
Ω
8.5
11.0
9.8
11.4
8.2
10.7
12.1
11.0
6.5
5.0
5.0
3.5
1.5
1.5
60
45
80
50
115
60
125
75
0.5
0.5
13.2
16.7
15.0
18.5
12.8
16.3
19.1
15.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
ns
ns
ns
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
(*)
50
40
65
45
1.0
1.0
1.5
1.5
MHz
t
OSLH
t
OSHL
Output to Output Skew
Time (note 1, 2)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
V
CC
(V)
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (note 1)
3.3
3.3
3.3
f
IN
= 10 MHz
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
T yp.
4
6
27
Max.
-40 to 85 C
Min.
Max.
o
Un it
pF
pF
pF
1) C
PD
isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
•
V
CC
•
f
IN
+ I
CC
/8(per circuit)
5/10
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