1 Mbit (128K x8) Page-Write EEPROM
SST29EE010
SST29EE / VE0101Mb (x8) Page-Write, Small-Sector flash memories
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 4.5-5.5V for SST29EE010
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs (typical)
• Fast Read Access Time
– 4.5-5.5V operation: 70 and 90 ns
– 2.7-3.6V operation: 150 and 200 ns
• Latched Address and Data
• Automatic Write Timing
•
– Internal V
PP
Generation
End of Write Detection
– Toggle Bit
– Data# Polling
Hardware and Software Data Protection
Product Identification can be accessed via
Software Operation
TTL I/O Compatibility
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm, 8mm x 20mm)
– 32-pin PDIP
All non-Pb (lead-free) devices are RoHS compliant
•
•
•
•
•
•
PRODUCT DESCRIPTION
The SST29EE010 is a 128K x8 CMOS Page-Write
EEPROMs manufactured with SST’s proprietary, high-per-
formance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST29EE010 write with a single power
supply. Internal Erase/Program is transparent to the user.
The SST29EE010 conform to JEDEC standard pinouts for
byte-wide memories.
Featuring high performance Page-Write, the SST29EE010
provides a typical Byte-Write time of 39 µsec. The entire
memory, i.e., 128 Kbyte, can be written page-by-page in as
little as 5 seconds, when using interface features such as
Toggle Bit or Data# Polling to indicate the completion of a
Write cycle. To protect against inadvertent write, the
SST29EE010 has on-chip hardware and Software Data
Protection schemes. Designed, manufactured, and tested
for a wide spectrum of applications, the SST29EE010 is
offered with a guaranteed Page-Write endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
The SST29EE010 is suited for applications that
require convenient and economical updating of pro-
gram, configuration, or data memory. For all system
applications, the SST29EE010 significantly improves
performance and reliability, while lowering power con-
sumption. The SST29EE010 improves flexibility while
lowering the cost for program, data, and configuration
storage applications.
To meet high density, surface mount requirements, the
SST29EE010 is offered in 32-lead PLCC and 32-lead
TSOP packages. A 600-mil, 32-pin PDIP package is also
available. See Figures 2, 3, and 4 for pin assignments.
Device Operation
The SST Page-Write EEPROM offers in-circuit electrical
write capability. The SST29EE010 does not require sepa-
rate Erase and Program operations. The internally timed
Write cycle executes both erase and program transparently
to the user. The SST29EE010 has industry standard
optional Software Data Protection, which SST recom-
mends always to be enabled. The SST29EE010 is com-
patible with industry standard EEPROM pinouts and
functionality.
©2009 Silicon Storage Technology, Inc.
S71061-13-000
3/09
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 Mbit Page-Write EEPROM
SST29EE010
Data Sheet
Read
The Read operations of the SST29EE010 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 5).
writing to the selected page and will leave the
SST29EE010 protected at the end of the Page-Write. The
page-load cycle consists of loading 1 to 128 bytes of data
into the page buffer. The internal Write cycle consists of the
T
BLCO
time-out and the write timer operation. During the
Write operation, the only valid reads are Data# Polling and
Toggle Bit.
The Page-Write operation allows the loading of up to 128
bytes of data into the page buffer of the SST29EE010
before the initiation of the internal Write cycle. During the
internal Write cycle, all the data in the page buffer is written
simultaneously into the memory array. Hence, the Page-
Write feature of SST29EE010 allows the entire memory to
be written in as little as 5 seconds. During the internal Write
cycle, the host is free to perform additional tasks, such as to
fetch data from other locations in the system to set up the
write to the next page. In each Page-Write operation, all the
bytes that are loaded into the page buffer must have the
same page address, i.e. A
7
through A
16
. Any byte not
loaded with user data will be written to FFH.
See Figures 6 and 7 for the Page-Write cycle timing dia-
grams. If after the completion of the three-byte SDP load
sequence or the initial byte-load cycle, the host loads a sec-
ond byte into the page buffer within a byte-load cycle time
(T
BLC
) of 100 µs, the SST29EE010 will stay in the page-
load cycle. Additional bytes are then loaded consecutively.
The page-load cycle will be terminated if no additional byte
is loaded into the page buffer within 200 µs (T
BLCO
) from
the last byte-load cycle, i.e., no subsequent WE# or CE#
high-to-low transition after the last rising edge of WE# or
CE#. Data in the page buffer can be changed by a subse-
quent byte-load cycle. The page-load period can continue
indefinitely, as long as the host continues to load the device
within the byte-load cycle time of 100 µs. The page to be
loaded is determined by the page address of the last byte
loaded.
Write
The Page-Write to the SST29EE010 should always use
the JEDEC Standard Software Data Protection (SDP)
three-byte command sequence. The SST29EE010 con-
tains the optional JEDEC approved Software Data Protec-
tion scheme. SST recommends that SDP always be
enabled, thus, the description of the Write operations will
be given using the SDP enabled format.
The three-byte
SDP Enable and SDP Write commands are identical;
therefore, any time a SDP Write command is issued,
Software Data Protection is automatically assured.
The
first time the three-byte SDP command is given, the device
becomes SDP enabled. Subsequent issuance of the same
command bypasses the data protection for the page being
written. At the end of the desired Page-Write, the entire
device remains protected. For additional descriptions,
please see the application notes,
The Proper Use of
JEDEC Standard Software Data Protection
and
Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories.
The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE010. Steps 1 and 2 use the same timing for both
operations. Step 3 is an internally controlled Write cycle for
writing the data loaded in the page buffer into the memory
array for nonvolatile storage. During both the SDP three-
byte load sequence and the byte-load cycle, the addresses
are latched by the falling edge of either CE# or WE#,
whichever occurs last. The data is latched by the rising
edge of either CE# or WE#, whichever occurs first. The
internal Write cycle is initiated by the T
BLCO
timer after the
rising edge of WE# or CE#, whichever occurs first. The
Write cycle, once initiated, will continue to completion, typi-
cally within 5 ms. See Figures 6 and 7 for WE# and CE#
controlled Page-Write cycle timing diagrams and Figures
16 and 18 for flowcharts.
The Write operation has three functional cycles: the Soft-
ware Data Protection load sequence, the page-load cycle,
and the internal Write cycle. The Software Data Protection
consists of a specific three-byte load sequence that allows
©2009 Silicon Storage Technology, Inc.
Software Chip-Erase
The SST29EE010 provides a Chip-Erase operation, which
allows the user to simultaneously clear the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
The Software Chip-Erase operation is initiated by using a
specific six-byte load sequence. After the load sequence,
the device enters into an internally timed cycle similar to the
Write cycle. During the Erase operation, the only valid read
is Toggle Bit. See Table 4 for the load sequence, Figure 11
for timing diagram, and Figure 20 for the flowchart.
S71061-13-000
3/09
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1 Mbit Page-Write EEPROM
SST29EE010
Data Sheet
Write Operation Status Detection
The SST29EE010 provides two software means to detect
the completion of a Write cycle, in order to optimize the sys-
tem Write cycle time. The software detection includes two
status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The
End-of-Write detection mode is enabled after the rising
WE# or CE# whichever occurs first, which initiates the
internal Write cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29EE010 provides the JEDEC approved optional
Software Data Protection scheme for all data alteration
operations, i.e., Write and Chip-Erase. With this scheme,
any Write operation requires the inclusion of a series of
three-byte load operations to precede the data loading
operation. The three-byte load sequence is used to initiate
the Write cycle, providing optimal protection from inadvert-
ent Write operations, e.g., during the system power-up or
power-down. The SST29EE010 is shipped with the Soft-
ware Data Protection disabled.
The software protection scheme can be enabled by apply-
ing a three-byte sequence to the device, during a page-
load cycle (Figures 6 and 7). The device will then be auto-
matically set into the data protect mode. Any subsequent
Write operation will require the preceding three-byte
sequence. See Table 4 for the specific software command
codes and Figures 6 and 7 for the timing diagrams. To set
the device into the unprotected mode, a six-byte sequence
is required. See Table 4 for the specific codes and Figure
10 for the timing diagram. If a write is attempted while SDP
is enabled the device will be in a non-accessible state for
~300 µs. SST recommends Software Data Protection
always be enabled. See Figure 18 for flowcharts.
The SST29EE010 Software Data Protection is a global
command, protecting all pages in the entire memory array
once enabled. Therefore using SDP for a single Page-
Write will enable SDP for the entire array. Single pages by
themselves cannot be SDP enabled.
Single power supply reprogrammable nonvolatile memo-
ries may be unintentionally altered. SST strongly recom-
mends that Software Data Protection (SDP) always be
enabled. The SST29EE010 should be programmed using
the SDP command sequence.
Data# Polling (DQ
7
)
When the SST29EE010 is in the internal Write cycle, any
attempt to read DQ
7
of the last byte loaded during the byte-
load cycle will receive the complement of the true data.
Once the Write cycle is completed, DQ
7
will show true
data. Note that even though DQ
7
may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. See Fig-
ure 8 for Data# Polling timing diagram and Figure 17 for a
flowchart.
Toggle Bit (DQ
6
)
During the internal Write cycle, any consecutive attempts to
read DQ
6
will produce alternating ‘0’s and ‘1’s, i.e. toggling
between 0 and 1. When the Write cycle is completed, the
toggling will stop. The device is then ready for the next
operation. See Figure 9 for Toggle Bit timing diagram and
Figure 17 for a flowchart. The initial read of the Toggle Bit
will typically be a “1”.
Data Protection
The SST29EE010 provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
©2009 Silicon Storage Technology, Inc.
S71061-13-000
3/09
3
1 Mbit Page-Write EEPROM
SST29EE010
Data Sheet
Please refer to the following Application Notes for more
information on using SDP:
•
•
Protecting Against Unintentional Writes When
Using Single Power Supply Flash Memories
The Proper Use of JEDEC Standard Software
Data Protection
TABLE 1: Product Identification
Address
Manufacturer’s ID
Device ID
SST29EE010
0001H
07H
T1.4 1061
Data
BFH
0000H
Product Identification
The Product Identification mode identifies the device
as the SST29EE010 and manufacturer as SST. This
mode is accessed via software. For details, see Table
4, Figure 12 for the software ID entry and read timing
diagram and Figure 19, for the ID entry command
sequence flowchart.
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Software ID Exit (reset) opera-
tion, which returns the device to the Read operation. The
Reset operation may also be used to reset the device to the
Read mode after an inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. See Table 4 for software command
codes, Figure 13 for timing waveform, and Figure 19 for a
flowchart.
X-Decoder
SuperFlash
Memory
A
16
- A
0
Address Buffer & Latches
Y-Decoder and Page Latches
CE#
OE#
WE#
Control Logic
I/O Buffers and Data Latches
DQ
7
- DQ
0
1061 B1.0
FIGURE 1: Functional Block Diagram
©2009 Silicon Storage Technology, Inc.
S71061-13-000
3/09
4
1 Mbit Page-Write EEPROM
SST29EE010
Data Sheet
WE#
VDD
A12
A15
A16
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
4
3
2
1
32 31 30
29
28
27
26
25
24
23
22
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
1061 32-plcc P01.0
32-lead PLCC
Top View
21
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
FIGURE 2: Pin Assignments for 32-lead PLCC
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1061 32-tsop F02.0
FIGURE 3: Pin Assignments for 32-lead TSOP
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
32-pin
6
PDIP
7
8
Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1061 32-pdip P03.0
FIGURE 4: Pin Assignments for 32-pin PDIP
©2009 Silicon Storage Technology, Inc.
S71061-13-000
3/09
5
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