256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)
Many-Time Programmable Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories
Data Sheet
FEATURES:
• Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8
• 4.5-5.5V Read Operation
• Superior Reliability
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Read Access Time
– 70 ns
– 90 ns
• Fast Byte-Program Operation
– Byte-Program Time: 20 µs (typical)
– Chip Program Time:
0.7 seconds (typical) for SST27SF256
1.4 seconds (typical) for SST27SF512
2.8 seconds (typical) for SST27SF010
5.6 seconds (typical) for SST27SF020
• Electrical Erase Using Programmer
– Does not require UV source
– Chip-Erase Time: 100 ms (typical)
• TTL I/O Compatibility
• JEDEC Standard Byte-wide EPROM Pinouts
• Packages Available
– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 28-pin PDIP for SST27SF256/512
– 32-pin PDIP for SST27SF010/020
PRODUCT DESCRIPTION
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /
128K x8 / 256K x8 CMOS, Many-Time Programmable
(MTP) low cost flash, manufactured with SST’s proprietary,
high performance SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. These MTP devices can be electrically erased
and programmed at least 1000 times using an external pro-
grammer with a 12 volt power supply. They have to be
erased prior to programming. These devices conform to
JEDEC standard pinouts for byte-wide memories.
Featuring high performance Byte-Program, the
SST27SF256/512/010/020 provide a Byte-Program time of
20 µs. Designed, manufactured, and tested for a wide
spectrum of applications, these devices are offered with an
endurance of at least 1000 cycles. Data retention is rated at
greater than 100 years.
The SST27SF256/512/010/020 are suited for applications
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
To meet surface mount and conventional through hole
requirements, the SST27SF256/512 are offered in 32-pin
PLCC, 32-pin TSOP and 28-pin PDIP packages. The
,
SST27SF010/020 are offered in 32-pin PDIP 32-pin PLCC
,
and 32-pin TSOP packages. See Figures 1, 2, and 3 for
pinouts.
©2001 Silicon Storage Technology, Inc.
S71152-02-000 5/01
502
1
Device Operation
The SST27SF256/512/010/020 are a low cost flash solu-
tion that can be used to replace existing UV-EPROM, OTP
,
and mask ROM sockets. These devices are functionally
(read and program) and pin compatible with industry stan-
dard EPROM products. In addition to EPROM functionality,
these devices also support electrical erase operation via an
external programmer. They do not require a UV source to
erase, and therefore the packages do not have a window.
Read
The Read operation of the SST27SF256/512/010/020 is
controlled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (T
CE
). Data is available at the
output after a delay of T
OE
from the falling edge of OE#,
assuming that CE# pin has been low and the addresses
have been stable for at least T
CE
- T
OE
. When the CE# pin
is high, the chip is deselected and a typical standby current
of 10 µA is consumed. OE# is the output control and is
used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Byte-Program Operation
The SST27SF256/512/010/020 are programmed by using
an external programmer. The programming mode for
SST27SF256/010/020 is activated by asserting 12V (±5%)
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MTP is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
on V
PP
pin, V
DD
= 5V (±5%), V
IL
on CE# pin, and
V
IH
on
OE# pin. The programming mode for SST27SF512 is acti-
vated by asserting 12V (±5%) on OE#/V
PP
pin, V
DD
= 5V
(±5%), and V
IL
on CE# pin. These devices are pro-
grammed byte-by-byte with the desired data at the desired
address using a single pulse (CE# pin low for
SST27SF256/512 and PGM# pin low for SST27SF010/
020) of 20 µs. Using the MTP programming algorithm, the
Byte-Programming process continues byte-by-byte until
the entire chip has been programmed.
Product Identification Mode
The Product Identification mode identifies the devices as
the SST27SF256, SST27SF512, SST27SF010 and
SST27SF020 and manufacturer as SST. This mode may
be accessed by the hardware method. To activate this
mode for SST27SF256/010/020, the programming equip-
ment must force V
H
(12V±5%) on address A
9
with V
PP
pin
at V
DD
(5V±10%) or V
SS
. To activate this mode for
SST27SF512, the programming equipment must force V
H
(12V±5%) on address A
9
with OE#/V
PP
pin at V
IL
. Two
identifier bytes may then be sequenced from the device
outputs by toggling address line A
0
. For details, see Tables
3, 4, and 5 for hardware operation.
TABLE 1: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST27SF256
SST27SF512
SST27SF010
SST27SF020
0001H
0001H
0001H
0001H
A3H
A4H
A5H
A6H
T1.1 502
Chip-Erase Operation
The only way to change a data from a “0” to “1” is by electri-
cal erase that changes every bit in the device to “1”. Unlike
traditional EPROMs, which use UV light to do the Chip-
Erase, the SST27SF256/512/010/020 uses an electrical
Chip-Erase operation. This saves a significant amount of
time (about 30 minutes for each Erase operation). The
entire chip can be erased in a single pulse of 100 ms (CE#
pin low for SST27SF256/512 and PGM# pin for
SST27SF010/020). In order to activate the Erase mode for
SST27SF256/010/020, the 12V (±5%) is applied to V
PP
and A
9
pins, V
DD
= 5V (±5%), V
IL
on CE# pin, and
V
IH
on
OE# pin. In order to activate Erase mode for SST27SF512,
the 12V (±5%) is applied to OE#/V
PP
and A
9
pins, V
DD
=
5V (±5%), and V
IL
on CE# pin. All other address and data
pins are “don’t care”. The falling edge of CE# (PGM# for
SST27SF010/020) will start the Chip-Erase operation.
Once the chip has been erased, all bytes must be verified
for FFH. Refer to Figures 13, 14, and 15 for the flowcharts.
Data
BFH
0000H
©2001 Silicon Storage Technology, Inc.
S71152-02-000 5/01
502
2
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