CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETERS
Power Supply Current: S1 = 2
At T
A
= -40
o
C to +85
o
C, Unless Otherwise Specified
SYMBOL
I
CCH
I
CCL
TEST CONDITIONS
Control = High (Output On)
Control = Low (Output Off)
Thd. Voltage, High
Thd. Voltage, Low
Hysteresis
Leakage, 0.0 to 5.5V
Output Saturation Voltage, I
CC1
= 200mA,
V
CONTROL
= High
Collector Output Leakage, V
CONTROL
=
Low
V
SENSE
= High, I
FLAG
= 3mA
Output Leakage, V
CC
= V
FLAG
= 10V
Control In to Drive Out
Drive Off to Flag Off
Flag Delay from Control In
MIN
-
-
-
0.9
0.4
-20
-
TYP
-
-
-
-
0.65
-
-
MAX
25
5
3.5
-
2.0
+20
0.5
UNITS
mA
mA
V
V
V
µA
V
Control Input: S1 = 3
V
THDH
V
THDL
V
THDH
-V
THDL
I
IL
Driver In, Out (Pin 6, 5): S1 = 3
V
SAT
I
LEAK
-
-
100
µA
Flag Output Low: S1 = 2
Flag Output High: S1 = 3
Prop. Delay: S1 = 1
V
FSAT
V
FLEAK
t
ON
, t
OFF
t
FLAG
t
D
-
-
-
-
150
310
50
-
-
5
10
-
335
-
0.8
10
-
-
600
360
-
V
µA
µs
µs
µs
mV
dB
Sense Input Thd. Level: S1 = 1
Power Supply Rejection Ratio
NOTES:
V
SENTHD
PSSR
1. Refer to Figure 3 Test Diagram for electrical test connections.
2. Refer to Figure 2 Timing Diagram for logic switching and prop delay.
3. Unless otherwise specified: V
CC
= V
CC1
= V
CC2
= 7V to 10V;
V
SENSE
= “Low”; V
CONTROL
= “Low”;
Control in levels are defined as “Low” equals 0.0V and “High” equals 5.0V.
10-42
CA3274
t
RISE
t
FALL
t
ON
DELAY
CONTROL IN - PIN 7
t
OFF
DELAY
DRIVE OUT- PIN 5
CURRENT
LIMITING
ON TIME
SYSTEM
NOISE
3.35mV
SENSE
LEVEL
SENSE IN - PIN 2
t
SENSE
FLAG OUT- PIN 1
(NOISE HOLD-OFF
DELAY)
OUTPUT
LOAD CURRENT
t
D
(SEE NOTE)
t
FLAG
NOTE: For V
CC
= 7V to 10V; t
D
(MAX) = 600µS, if Control In = High,
Sense In = High; Pin 1, Flag Out can go low only if t
SENSE
≥
t
D
DELAY
FIGURE 2. CA3274 TIMING DIAGRAM
POWER SUPPLY
+V
CC
I
CC
OUTPUT LOAD
POWER SUPPLY
+V
CC1
8
IN
6 IN
51Ω
(ADJ. FOR 200mA
IN V
SAT
TEST)
1
S1
3
IN V
CONTROL
+V
CC2
(ADJ. FOR 3mA
IN FLAG-OUT
V
SAT
TEST
FLAG
OUT
7
CONTROL
LOGIC
Q2
DRIVER
5
OUT
(PSSROUT)
2.1V
10K
1
2
SENSE S1
IN
3
1
2.1V
120Ω
120
-
4
Q1
LATCH
+
SIGNAL
GROUND
335mV
V
SENSE
3
POWER
GROUND
FIGURE 3. CA3274 TEST CIRCUIT
10-43
CA3274
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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